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Message
From: "H. Peter Anvin" <hpa@z...>
Date: Thu, 25 Sep 2003 13:52:17 -0700
Subject: [oc] T80 and IM2
Hello friends,
Are there any known problems or timing abberations with the T80 core in
IM 2? I have a design which exhibits the following problem:
* For each interrupt, there is some probability (perhaps 15%) that it
goes off to vector FF instead of the proper vector.
* Probes on the T80 interface shows that Di contains the correct value
(34h) in the last cycle M1_n = 0, IORQ_n = 0, but that the CPU then
starts fetching bytes from I:FFh instead of I:34h.
I have tried artificially extend the time during with Di is "driven" for
an INTAK by one cycle; no effect. "Driven" here means that the
interrupting I/O device -- a PIO model -- puts a value other than FFh on
its output; I have adopted the convention that all devices output FFh
when they would be tristated on a real system; the outputs are then all
ANDed together to form the Di input to the CPU.
-hpa
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