|
Message
From: Joachim Strömbergson<Joachim.Strombergson@I...>
Date: Mon, 22 Sep 2003 14:02:14 +0200
Subject: Re: [oc] Free Place & Route
Aloha!
Bill Cox wrote:
> The world is looking for a higher level design environment to help
> address the "productivity gap". Most guys in the past have focused on
> "behavioral compilers". These things figure out how to pipeline a
> design for you. Basically, these tools harm our ability to understand
> and control the synthesis process. A cycle based aproach is lower
> level, but it keeps the designer involved where he's needed: deciding
> what data gets computed, and when.
Behavioural compilers have been replaced with a shift towards component based
SoC designs. In other words, the productivity gap is handled by using more
complex building blocks, not writing behavoural code.
> ASIC designers know that writing a C simulation model is a great way to
> prototype a new design. The simulation is fast, and easy to write.
> These simulations, in my experience, are generally cycle based.
>
> Why not synthesize them directly?
Because you lack information about the physical world at the C-level. RTL is
the highest level were physical information is handled. RTL will clearly
prevail at the 90 nm node and below. The latest development reported by EE
Times is that wires/routing might be the next big thing at RTL. Lots of talks
about virtual prototyping at RTL level.
And no, C does not contain a good abstraction for wires and routing.
--
Med vänlig hälsning, Yours
Joachim Strömbergson - Alltid i harmonisk svängning.
VP, Research & Development
----------------------------------------------------------------------
InformAsic AB / Hugo Grauers gata 5B / SE-411 33 GÖTEBORG / Sweden
Tel: +46 31 68 54 90 Fax: +46 31 68 54 91 Mobile: +46 733 75 97 02
E-mail: joachim.strombergson@i... Home: www.informasic.com
----------------------------------------------------------------------
|
 |
Browse
