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Message
From: John Kent <jekent@o...>
Date: Sun, 21 Sep 2003 13:41:07 +1000
Subject: Re: [oc] Mathematical modeling of FPGA functions
Hi Antti,
I'll take this conversation off line with you. I'm interested in finding
out how
Labview tackle to problem. ie whether they actually generate logic from
a programming language or if they have pre-built parametrically controlled
modules.
The problem as I see it is as much to do with sheduling of the hardware
as just rolling out parallel hardware. If you have a loop in a pipeline
of hardware,
then there is the problem of priming the loop so the pipeline is always
full,
or at least padding out branches of the pipeline with null operations.
I remember reading an example of that in texas instruments TMS320C6100 (?)
DSP application manual somewhere.
In the 90s I had a play with occam and parallel C and there was a bit of
work to
generate hardware from them. Parallel C and Occam both left the execution
scheduling to the programmer by using PAR (parallel) and SEQ (sequential)
statements. Some of the work involved using a one hot state machine for the
sequential statement and logic to fork and synchronise parallel threads.
I'm sure its possible to use dependancy graphs to determine the scheduling
and interdependancy of variables is a C program without having to go
to explicity stating it in the program, but it would involve re-writting a
complete compiler to add that information though.
John.
antti@c... wrote:
>Hm,
>
>I just happen to evaluate the LabView FPGA board and tools
>right now.
>
>LabView/FPGA includes full Xilinx ISE
>there is a compile server (written in LabView)
>normal Labview is used for design (selecting FPGA target!)
>the compile is sent to server, the server generates a build
>script and launches xilinx implementation tools
>the VHDL file are deleted at the end of the batch, but
>during synthesis they are all visible in the /temp
>directory :)
>
>so it is possible to look at VHDL that NI generates from
>Labview diagrams.
>(I have not done that yet, not sure if it makes sense)
>
>if scilab would export vhdl would defenetly be nice :)
>
>antti
>
>
>
>
--
http://members.optushome.com.au/jekent
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