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Message
From: antti@c...
Date: Sat, 20 Sep 2003 16:08:43 +0200
Subject: Re: [oc] Mathematical modeling of FPGA functions
Hm,
I just happen to evaluate the LabView FPGA board and tools
right now.
LabView/FPGA includes full Xilinx ISE
there is a compile server (written in LabView)
normal Labview is used for design (selecting FPGA target!)
the compile is sent to server, the server generates a build
script and launches xilinx implementation tools
the VHDL file are deleted at the end of the batch, but
during synthesis they are all visible in the /temp
directory :)
so it is possible to look at VHDL that NI generates from
Labview diagrams.
(I have not done that yet, not sure if it makes sense)
if scilab would export vhdl would defenetly be nice :)
antti
----- Original Message -----
From: John Kent <jekent@o... >
To: cores@o...
Date: Sat, 20 Sep 2003 12:19:48 +1000
Subject: [oc] Mathematical modeling of FPGA functions
>
>
>
> Hi,
>
> This question really follows on from the"free place & route"
> thread.
> I hear a lot about LabView providing simulation of things like
> filter design that can spit out a VHDL or Verilog design once the
> simulation is right. Given that I'm a home user, and don't have
> much money
> to spend on such things, I was wondering if it was possible to
> build
> a library under SCILAB, which is a free scientific functions
> package.
>
> http://www-rocq.inria.fr/scilab/
>
> I could not find any VHDL library functions for SCILAB and
> I'm not even sure if that is the best package to start with.
> I'd like to experiment with some adaptive equaliser algorithms and
> some image processing algorithms.
> It would be pretty neat to be able to simulate the design using
> VHDL library models, in something like SCILAB and then spit
> out the design at the end.
>
> I've heard a little about things like System C, but could not get
> the
> package to compile under cygwin.
>
> John.
>
> --
> http://members.optushome.com.au/jekent
>
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