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Message
From: Tom Hawkins <tom@l...>
Date: Sat, 20 Sep 2003 08:44:23 -0500
Subject: Re: [oc] Small CPU architectures
On Saturday 20 September 2003 01:53 am, Kirill 'Big K' Katsnelson
wrote:
> Guys,
>
> I am wondering why, when FPGA allows one to have infinite varieties
> of central (micro)processors, people keep implementing PIC, 8051
> and 68K. First, I think that by implementing a task-specific
> instruction set, one can end up with faster and smaller CPU.
This was the precise goal of the state space processor
(http://www.opencores.org/projects/cf_ssp/). I needed a small
processor for a real-time control application that needed to fit on a
old Altera. Original it needed to calculate multivariable linear
functions, and hence the name "State Space". But midway through the
project we realized SSP could handle more tasks than just linear
functions. In the current application, SSP also performs a cordic
calculation.
SSP is not a Turing complete machine; there are no jump or branch
instructions. Rather, each instruction is executed one after another
until it hits "Halt". An external signal tells SSP when to execute a
program. In my case, it's a control sample calculation. Though it
is certainly not as flexible as a general purpose processor, it's
great for hard-real-time and space limited applications.
Even though SSP has no branch instructions, it does have a few
instructions for decisions: see "Switch", "AddCond", and "ShiftClip".
Switch made it possible to perform the cordic, and AddCond was
specifically tailored for booth multiplication (SSP has no hardware
multiplier).
I've implemented a more powerful version of SSP I've called TTP (TT
for "Time Triggered"). Among other features, it includes a general
purpose data memory. I'll probably upload it to OC soon.
-Tom
>
> I was looking for the subject, kind of research people do on
> "non-traditional" if you allow me to put it this way, CPU cores.
> To my surprise, I found practically no practical designs! I found
> a 4-bit micro with 4 different instructions that fits into a
> Coolrunner, and a proof that the Turing machine is implementable
> thus this is a general-purpose CPU... As far as going both novel
> and practical, no luck!
>
> For example, I *loved* the PDP-11 instructions set. When after
> VAXen there arrived the first PC/XTs, I wondered what type of
> instruction set does that 8086 beast have. Oh my, I should not!
> When I found out, I was shocked by its complexity and irregularity.
> It was disgusting! It was awful! After a very regular PDP-11
> instructions, seeing 8086 is not for the faint of heart!
>
> I think, for one, that it is one of the easiest-decodable CISC
> instruction sets possible. I looked for an FPGA implementation;
> besides one sold as a signle-board replacement for a PDP-11 (so it
> was the matter of necessity and not choice in their case) I found
> none at all!
>
> Anyway, it would be interesting to find out what kind of more or
> less open research is being made in this direction.
>
> -kkm
--
Tom Hawkins
Launchbird Design Systems, Inc.
952-200-3790
http://www.launchbird.com/
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