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Message
From: Bill Cox <bill@v...>
Date: Sat, 20 Sep 2003 03:40:59 -0400
Subject: Re: [oc] FREE Verilog Simulator
Rudolf Usselmann wrote:
>On Fri, 2003-09-19 at 20:42, Joachim Strömbergson wrote:
>
>
>>Aloha!
>>
>>Rudolf Usselmann wrote:
>>
>>
>>>I just stumbled across this baby:
>>>
>>>http://www.pragmatic-c.com/gpl-cver/
>>>
>>>
>>Pretty kewl. I compiled and built it without any problems. Kudos to the
>>Pragmatic-C team to produce a nice tarball with lots of READMEs explaining all
>>directories etc.
>>
>>I've done som initial testruns on it works. What I'm curious/concerned about
>>is simulation speed, especially on non-trivial designs. Icarus Verilog is in
>>my opinion quite good in this respect. If time permits I'll try and do a
>>shootout between these two Open Source Verilog simulators.
>>
>>
>
>Hi !
>
>I must say I find cver much more stable and faster than
>icarus. So far I have found only one bug in it and the
>authors immediately fixed it (there is a new release as
>of last night).
>
>
>
>
This looks good. It looks like the cver guys are offering a slower
version of their commercial simulator for free.
This will allow my company to offer free cver Verilog simulation with
our place and route tools for one-mask ASICs without having to throw
large ammounts of cash at anyone. For an upgrade, our users can just
buy the commercial version.
I'd recommend generally verifying Verilog cores on OpenCores with this
thing.
Bill
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