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Message
From: antti@c...
Date: Mon, 15 Sep 2003 13:12:18 +0200
Subject: Re: [oc] KRPAN: OC embbedded FPGA project [verilog2bitstream]
Hi Marko,
yes, I found that too, the MAP PLACE and ROUTE all do work !!
and it is pretty nicely 'visualized' so you can see it.
FYI the KRPAN is very close to CAL1024 (algotronix) CAL had
not 8 to 1 but 4 to 1 muxes and only neighbor connections.
(and simpler function block)
Question: could you please please add 2 things to KRPAN
(in minimal functionality)
1 IO pin locking
2 support for custom sizes of array, eg 8 x 8 GPC's
? I think it would no be too hard (for the authors at least)
as said KRPAN GPC is approx 26 slices so it is reasonable small
to be implemented in exisiting FPGAs.
if [1] and [2] from above are done then it is possible to make
a real working FPGA prototype.
the 18 by 18 array would not fit into medium size FPGAs so
I cant use the original KRPAN without modifications.
antti
----- Original Message -----
From: Marko Mlinar <markom@o... >
To: cores@o...
Date: Mon, 15 Sep 2003 10:53:29 +0200
Subject: Re: [oc] KRPAN: OC embbedded FPGA project
[verilog2bitstream]
>
>
> Antti,
>
> Yes, KRPAN project started at least 2 years ago from now. I didn't
> know any
> HDL then, but still I was hoping someone would write HDL model.
> For efficient FPGAs have to have custom desing and quite favorably
> custom FAB
> process ;) I guessed it was kinda too much for that time ;)
>
> Besides parser I think M&P&R tool should work nice. Code is
> also quite clean.
>
> Marko
>
> On Friday 12 September 2003 16:52, antti@c... wrote:
> > KRPAN seems to be sleeping?
> > just looked again at KRPAN place and route and it seems todo
> > something - well I only tested with very simple verilog
> designs.
> >
> > there was PROJECT HELP NEEDED - just for information for
> testing
> > I implemented GPC cell for Virtex (incl programming interface)
> it
> > takes 26 slices, so a small KRPAN array (8 x 8 GPC array)
> should
> > fit into medium size Virtex. So if only adding constraints to
> KRPAN
> > software it would be useable in real silicon :)
> >
> > antti
>
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