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Message
From: antti@c...
Date: Fri, 12 Sep 2003 16:52:56 +0200
Subject: [oc] KRPAN: OC embbedded FPGA project [verilog2bitstream]
KRPAN seems to be sleeping?
just looked again at KRPAN place and route and it seems todo
something - well I only tested with very simple verilog designs.
there was PROJECT HELP NEEDED - just for information for testing
I implemented GPC cell for Virtex (incl programming interface) it
takes 26 slices, so a small KRPAN array (8 x 8 GPC array) should
fit into medium size Virtex. So if only adding constraints to KRPAN
software it would be useable in real silicon :)
antti
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