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Message
From: Carl Witty <cwitty@n...>
Date: 09 Sep 2003 11:10:31 -0700
Subject: Re: [oc] Free Place & Route
On Tue, 2003-09-09 at 08:45, Bill Cox wrote:
> Of greater interest to me would be front end tools. Doesn't it seem
> strange to have opensource cores without any opensource tools to compile
> them? Can you get even bad synthesis cheap or free (without breaking
> any laws)?
There's Icarus Verilog (http://www.icarus.com/eda/verilog/), which does
synthesis and simulation. (I've never used it; I don't know anything
about the synthesis quality.)
I like, and use, JHDL (http://www.jhdl.org). This is, essentially, a
Java library for creating netlists; you write a program which creates a
netlist, and then compile and run it, and it produces an EDIF netlist.
The syntax is a little awkward compared to Verilog, but it's not nearly
as bad as you might fear.
I like JHDL because it's extremely powerful. It's easy to write
reusable components that are far more generic than the equivalent
Verilog; many of my components are generic not just on bit width, but
also on the number of input/output ports. I've also done things like
create my own "finite state machine" (FSM) module generator: my program
create a new FSM object, describe the FSM by making calls on the object,
and instantiate the FSM into a netlist.
And JDHL is open source.
> Another topic of interest to me is higher-level design entry. A
> cycle-based C-like environment could provide real gains IMO.
>
> If there's interest in doing a C-like cycle-based design language, I'll
> post more details.
I'm afraid I have no idea what a "C-like cycle-based design language"
might be, but I'm curious...
Carl Witty
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