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    Navigation: All forums > Cores > Message List > Message Post

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    From: Rudolf Usselmann <rudi@a...>
    Date: 07 Sep 2003 00:21:57 +0700
    Subject: [oc] Free Place & Route
    Top

    
    I don't know about you guys, but I always find it to
    be a pain in the neck using Xilinx or Altera back-end
    tools. I usually use a 3rd party Synthesis tool, but
    have no choice but to fight vendor proprietary tools
    for the back-end.
    
    So I would like to start a new project: The development
    of a FREE parameterizable Place & Route tool, that could
    be used with any FPGA architecture out there. Further,
    this tool MUST run under linux, other OS's optional.
    
    Now I am not a software guy so I can not write this, nor
    manage this project. But I am willing to put some cashe
    in to the project in terms of funding. What I have in mind
    is to hire a professional software team that can develop
    this project in a professional and timely manner. Of course
    the result of this project will be placed under GPL.
    However, I don't think I can finance a project of this
    magnitude on my own. Quite honestly I don't even have the
    slightest idea how much such a development would cost.
    
    So, I would like to start by specifying/outlining the
    features of such a tool, and then submit it for bidding
    to various software development companies for a quote.
    Once we have a quote I will try to raise money by begging
    all you good guys for donations !
    
    So what do you guys think of this so far ? Am I going
    crazy in my old days or will we all benefit from such
    a tool ? Do we have a chance to compete with the
    proprietary tools from the vendors ? Will they hate or
    love us ?
    
    I am thinking only to include support for Xilinx and
    Altera in the initial tool. This should capture well
    over 80% of the market. Since this will be all open
    source other FPGA vendors can add code to support
    their FPGA architectures as they wish.
    
    Would you guys be willing to donate some $$$ to such a
    project if you are guaranteed that it will come through ?
    
    First Round of Specifications
    -----------------------------
    - Accept a FPGA architecture description file
    - Accept EDIF netlist
    - No Synthesis Included
    - Accept a user constrain file
    - Do automatic place & route
    - Graphical Floorplaner/Editor
    - "bit-file" generator
    - support for various down-load cables/options
    
    Comments, Suggestions ?
    
    Best Regards, 
    rudi               
    ========================================================
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    Follow upAuthor
    Re: [oc] Free Place & RouteBill Cox
    Re: [oc] Free Place & RouteBill Cox
    Re: [oc] Free Place & RouteRudolf Usselmann
    Re: [oc] Free Place & RouteErez Birenzwig
    Re: [oc] Free Place & RouteTom Hawkins
    Re: [oc] Free Place & RouteShehryar Shaheen

     
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