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Message
From: antti@c...
Date: Mon, 28 Jul 2003 18:06:16 +0200
Subject: Re: [oc] 8051 and XSV
>
> Hi all,
>
> I am going to implement the oc8051 core at a xcv-300 board. I would
> like to know wich defines in the oc8051_defines.v file i should
> uncomment for it to work properly.
defines.v
//`define OC8051_RAM_XILINX
//`define OC8051_RAM_VIRTUALSILICON
`define OC8051_RAM_GENERIC
get correct generic_dpram (separate downlaod form cvs)
in generic_dpram
`define VENDOR_FPGA
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
thats it!
see result:
Writing NGDBUILD log file "oc8051_top.bld"...
NGDBUILD done.
Completed process "Translate".
Started process "Map".
Using target part "2vp7ff672-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...
Design Summary:
Number of errors: 0
Number of warnings: 129
Logic Utilization:
Number of Slice Flip Flops: 617 out of 9,856 6%
Number of 4 input LUTs: 3,007 out of 9,856 30%
Logic Distribution:
Number of occupied Slices: 1,867 out of 4,928 37%
Total Number 4 input LUTs: 3,368 out of 9,856 34%
Number used as logic: 3,007
Number used as a route-thru: 105
Number used for Dual Port RAMs: 256
(Two LUTs used per Dual Port RAM)
Number of bonded IOBs: 161 out of 396 40%
IOB Flip Flops: 77
Number of MULT18X18s: 1 out of 44 2%
Number of GCLKs: 1 out of 16 6%
Total equivalent gate count for design: 63,152
Additional JTAG gate count for IOBs: 7,728
antti
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