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Message
From: Atul Ware <baluware@y...>
Date: Sat, 21 Jun 2003 07:17:19 +0100 (BST)
Subject: Re: [oc] vhdl question
hi saumil ,
your problem is to just keep start high for two clocks or more..
so can just have delayed signals of read and or them with read...
this will solve your problem.
Example "start high for three clocks ":
clock_process:
( del1_read <= read;
del2_read <=del1_read; )
start <='1' when ((read or del1_read or del2_read ) = ' 1' and addr(7downto 0)="11111111" else '0';
If i am wrong please correct me...
Hey guys,
I had a question. I have a combinational statement in VHDL as given below.
start <= '1' when read='1' and addr(7 downto 0)="11111111" else '0';
Now what happens here is that read goes high only for one clock cycle and hence so does start. How can I make start stay high for 2 or more clock cycles and then go low ?
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Saumil Merchant
University of Tennessee
http://web.utk.edu/~smerchan
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