----- Original Message -----
Sent: Friday, June 20, 2003 10:01
AM
Subject: [oc] vhdl question
Hey guys,
I had a question. I have a combinational
statement in VHDL as given below.
start <= '1' when read='1' and addr(7 downto
0)="11111111" else '0';
Now what happens here is that read goes high only
for one clock cycle and hence so does start. How can I make start stay high
for 2 or more clock cycles and then go low ?
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Saumil
Merchant
University of Tennessee
http://web.utk.edu/~smerchan
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