|
Message
From: John Sheahan <jrsheahan@o...>
Date: 16 Jun 2003 21:31:33 +1000
Subject: Re: [oc] constraints while programming in VHDL
On Mon, 2003-06-16 at 22:11, ritika_dua@y... wrote:
>
>
> sir, i want to know how we can use delays in the vhdl code, as the
> delays can't be synthesized .
> --
they are useful in testbenches and models. Simulation in general.
But not in code to be synthesized.
Do I misunderstand the question?
john
.
|
Browse
