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Message
From: Uwe Bonnes <bon@e...>
Date: Mon, 16 Jun 2003 12:51:58 +0200
Subject: Re: [oc] constraints while programming in VHDL
>>>>> "ritika" == ritika dua <ritika_dua@y...> writes:
ritika> sir, i want to know how we can use delays in the vhdl code, as
ritika> the delays can't be synthesized .
Count clock cycles for delay, or go external and use a delay line.
Any other solution is problematic.
Bye
--
Uwe Bonnes bon@e...
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
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