|
Message
From: John Sheahan <jrsheahan@o...>
Date: 14 Jun 2003 10:50:22 +1000
Subject: Re: [oc] The use of both edge of the clock.
On Sat, 2003-06-14 at 01:46, nico@s... wrote:
> At school, we learn that design must be full synchronous on one edge of
> the clock to avoid any timing hasard.
>
> But, i see very often some chip interface that sample or deliver the data
> at the folling edge of the clock. Does this trick very usefull ? Does it
> generate dozen of "false path" for synthetiser ?
>
> What is the common rules and pitfall about using this ?
>
this trick is (well, was) very common in the datacomms world.
Sending data from one place to another on one edge - and sampling on
the other, can help a lot with setup and hold under the right
circumstances.
(usually those where things are slow enough that clock and data are sent
separately. Faster - embedded clock is the way to go)
john
|
 |
Browse
