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Message
From: Uwe Bonnes <bon@e...>
Date: Fri, 13 Jun 2003 17:54:54 +0200
Subject: Re: [oc] verilog CAN core implementation issues
>>>>> "anthonymarino" == anthonymarino <anthonymarino@i...> writes:
...
anthonymarino> WARNING:NgdBuild:526 - On the RAMB4_S8_S8 symbol
anthonymarino> "i_can_bsp/i_can_fifo/fifo", the following properties are
anthonymarino> undefined: INIT_00, INIT_01, INIT_02, INIT_03, INIT_04,
anthonymarino> INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A,
anthonymarino> INIT_0B, INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default
anthonymarino> value of all zeroes will be used.
Harmless: A warning that you didn't specified default values for the
blockram
anthonymarino> ERROR:NgdBuild:604 -
anthonymarino> logical block 'i_can_registers' with type
anthonymarino> 'can_registers'is unexpanded. Symbol 'can_registers' is
anthonymarino> not supported in target 'spartan2'.
This looks fishy. Try to understand what the author wanted to do. Probably
the syntax is problematic.
anthonymarino> WARNING:NgdBuild:454
anthonymarino> - logical net 'set_bus_error_irq' has no load
anthonymarino> WARNING:NgdBuild:452 - logical net 'tx_request' has no
anthonymarino> driver WARNING:NgdBuild:452 - logical net 'tx_data_4<0>'
anthonymarino> has no driver
"no driver" means that you use a signal where there is no gate that provides
the output. Probably some typing error.
"no load" means that some signal is generated, but never consumed.
Try to understand all those issues.
Bye
--
Uwe Bonnes bon@e...
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
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