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From: anthonymarino@i...
Date: Fri, 13 Jun 2003 16:22:19 -0100
Subject: [oc] verilog CAN core implementation issues

I am using Xilinx Foundation 4.2i to implement the verilog CAN core to a 
Xilinx Spartan2 XC2S200 FPGA. When I try to implement I get the 
following error and warnings:

WARNING:NgdBuild:526 - On the RAMB4_S8_S8 
symbol "i_can_bsp/i_can_fifo/fifo",
   the following properties are undefined: INIT_00, INIT_01, INIT_02, 
INIT_03,
   INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, 
INIT_0B,
   INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will 
be
   used.
ERROR:NgdBuild:604 - logical block 'i_can_registers' with 
type 'can_registers'is unexpanded. Symbol 'can_registers' is not 
supported in target 'spartan2'.
WARNING:NgdBuild:454 - logical net 'set_bus_error_irq' has no load
WARNING:NgdBuild:452 - logical net 'tx_request' has no driver
WARNING:NgdBuild:452 - logical net 'tx_data_4<0>' has no driver

This is just a sample of the numerous warnings. Does anyone have any 
suggestions. The Xilinx answer database has not been very helpful. 
Thank you.

Anthony Marino
Graduate Student
Rowan University
Glassboro, NJ

Follow up	Author
Re: [oc] verilog CAN core implementation issues	Uwe Bonnes