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Message
From: Jason Silcox <jsilcox@y...>
Date: Sun, 8 Jun 2003 15:54:49 -0700 (PDT)
Subject: Re: [oc] VHDL Help...
I've tried to do this exact "trick"...
When you try to synthesize this entity it will fail...
IEEE.MATH_REAL is not implemented in most synthesis
tools and thus the CEIL and LOG2 functions will not
be found...
I figured the synthesis tool would evaluated the
expression first and when it realized it was a constant
it wouldn't need a synthesizable model of the MATH_REAL
functions, but that was not the case...
If anyone does create a synthesizable version of this,
please e-mail it too me...
Thanks,
---
Jason Silcox
--- Shehryar Shaheen <shehryar.shaheen@u...> wrote:
> Try this
>
> LIBRARY IEEE;
> USE IEEE.STD_LOGIC_1164.ALL;
> USE IEEE.STD_LOGIC_ARITH.ALL;
> USE IEEE.STD_LOGIC_UNSIGNED.ALL;
> USE IEEE.MATH_REAL.ALL; <-- Add this package
>
> ENTITY mux IS
> GENERIC( size_data : integer := 8 );
> PORT(
> data : IN STD_LOGIC_VECTOR(size_data-1 downto 0);
> sel : IN STD_LOGIC_VECTOR(integer(ceil(log2(real(
> size_data)))) downto 0); <-- Put this line in place
> result : OUT STD_LOGIC
> );
> END mux;
>
> This should work if your compiler is VHDL93 compliant
> in case you are using modelsim complie it with these switches
>
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