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Message
From: John Sheahan <jrsheahan@o...>
Date: Tue, 29 Apr 2003 21:02:12 +1000
Subject: Re: [oc] test_bench
On Tue, Apr 29, 2003 at 10:40:41AM -0100, leire.rubio@a... wrote:
> Hello, I would like to know more about test_benches. What are they for?
the test bench is the structure used to exercise and hence verify
the design.
> Are they only for simulation or can be used for verification?
simulation.
verification is a more general area, simulation is one way.
> Are they
> placed into the FPGA?
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