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Message
From: Niclas Hedhman <niclas@h...>
Date: Tue, 29 Apr 2003 11:13:57 -0800
Subject: Re: [oc] Async reset: active high or active low?
On Monday 28 April 2003 01:31 pm, John Sheahan wrote:
> On Mon, Apr 28, 2003 at 05:24:40PM +0200, cyrano@n... wrote:
> > I really ask why active low reset is used in our labs. It was answer that
> > it is an historical raison because in TTL high level signal consumme less
> > energy than low one. Power up is not concerne any more because logic
> > begin to work at ~2.5 V.
>
> this is wrong. TTL inputs (real ttl, not this newfangled LS
> rubbish :) drew about 1.4ma when low and and few hundred microamps
> high. So an active low reset minimized power.
> (note that using minimize power and TTL in the same sentance is tricky)
;o)
Alternatives to "minimize";
- less wasting
- reduced
- optimized
Cyrano got part of the answer right, just that Reset is normally "off", i.e.
"high" and drew less current.
The argument of "reset by default at power-up" by a simple RC network, is a
more recent thing (I think?), in ultra-low cost designs, such as PIC12xx,
where a reset device cost more than the CPU (!).
(Paraphrasing; Using "I" and "think" in the same sentence is tricky.)
Niclas
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