|
Message
From: Rudolf Usselmann <rudi@a...>
Date: 28 Apr 2003 12:39:08 +0700
Subject: Re: [oc] Async reset: active high or active low?
On Mon, 2003-04-28 at 05:17, cyrano@n... wrote:
> Haytham Azmi <haythamazmi@h...> a écrit :
>
> > Hi Nicolas ,
> > I don't agree with you , i think it must be active high for
> > many reasons ..
> > 1- At power up it's normal for all system to reset , this is
> > the normal case and then , start executing the main
> > program .
>
> The power up signal start from 0v. If the signal is active high, the reset
> is only established after the end of the ramp up of the power supply with
Nonsense ! Reset will always be valid AFTER the power-up ramp and
Vcc_min has been reached.
Specially the case you are describing. Think about it: in order
to bring in a low active reset which is externally low active
as well, you need a non-inverting input buffer. Last time I
check a non-inverting buffer consists of two inverters back-to-back.
Further you make the assumption that the flops output will stay
at ground level when the async reset is asserted while Vcc is in
an undefined state. Third you make the assumption that the Tri-state
buffer will actually properly turn off while Vcc is undefined.
Sorry, I don't mean to be harsh but that just won't work. You
would have to do a complete spice analysis of your chips reset
and network and the attached I/O buffers to make your suggestion
work. And we haven't talked about the internal reset network and
it's buffers yet.
> the risk of undefined value on other pin during the ramp up. This could be
> dangerous (bus contention,...).
>
>
Two solutions for you here:
1) Ignore the bus contention during power-up all together.
Modern output buffers have current limiters built in and
are "short prove/resistant". E.g. your chip will not die
from it and will not kill other older chips that are attached
to it's bus.
2) If you really want an elegant solution to avoid bus
contention, separate the power rings for I/Os and the
core. Clock and Reset inputs should have either their
own power connection or be powered from the core. Require
that the core (and the reset and clock pins) is powered
up first. Most processes these days already provide separate
power for core and IOs. So all you have to do is explain
in your documentation how the chip should be powered up to
avoid contentions.
Regards,
rudi
-------------------------------------------------------
www.asics.ws -- Solutions for your ASIC/FPGA needs ---
---------------- FPGAs * Full Custom ICs * IP Cores ---
* * * FREE IP Cores --> http://www.asics.ws/ <-- * * *
|
 |
Browse
