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Message
From: <cyrano@n...>
Date: Sun, 27 Apr 2003 22:17:08 CEST
Subject: Re: [oc] Async reset: active high or active low?
Haytham Azmi <haythamazmi@h...> a écrit :
> Hi Nicolas ,
> I don't agree with you , i think it must be active high for
> many reasons ..
> 1- At power up it's normal for all system to reset , this is
> the normal case and then , start executing the main
> program .
The power up signal start from 0v. If the signal is active high, the reset is only established after the end of the ramp up of the power supply with the risk of undefined value on other pin during the ramp up. This could be dangerous (bus contention,...).
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