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    Navigation: All forums > Cores > Message List > Message Post

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    From: "Haytham Azmi" <haythamazmi@h...>
    Date: Sun, 27 Apr 2003 10:48:20 +0300
    Subject: Re: [oc] Async reset: active high or active low?
    Top

    
    Hi Nicolas ,
               I don't agree with you , i think it must be active high for
               many reasons ..
               1- At power up it's normal for all system to reset , this is
                  the normal case and then , start executing the main
                  program .
               2- If we put the reset active low , that means you have to
                  put high at the reset signal during normal mode , and
                  that will be a sourcefor power loss ... so it's better
                  to make it active high .
               3- I think you can check for any microcontrolle datasheet
                  you will see that the reset is active high .
    
                  If iam wrong please correct my information.
    
                                                      Best redards,
                                                         Haytham
    
    
    
    
    
    
    >From: <cyrano@n...>
    >Reply-To: cores@o...
    >To: <cores@o...>
    >Subject: Re: [oc] Async reset: active high or active low?
    >Date: Sat, 26 Apr 2003 23:50:26 CEST
    >
    >Active low signal are to avoid potential problem at power up. So when the 
    >power goes up, the chip are protected because the reset is at zero.
    >
    >For sync/async reset,where i work we use async set (known state before the 
    >establishing of the clock) and sync release (to avoid metastability).
    >
    >
    >Nicolas Boulay
    >
    >Allan Herriman <allan_herriman@a...> a écrit :
    >
    > > Hi,
    > >    I'm readying a core for publication on opencores, so I thought I'd
    > > better check it against the opencores coding standards (since I usually
    > > write against a proprietary internal coding standard).
    > >
    > > I found there were a few contradictory coding standards documents on the
    > > opencores web site.  In particular, I found one saying that the async
    > > reset signal should be active high, and another saying it should be
    > > active low.  I found one that said it should be active high, then gave
    > > some example code with an active low reset.
    > > (The good thing about standards is that there are so many to choose 
    >from.)
    > >
    > > So I thought I'd look at some code in some projects.  You guessed it, a
    > > mixture of active high and active low.  (My sample was very small, so I
    > > may have missed the trend.)
    > >
    > > I realise that the actual polarity doesn't matter that much (since it
    > > can be inverted in the instantiation), but which is the "right" way to
    > > do it from the opencores perspective?  Active high or active low?
    > >
    > > BTW, my vote's for active high signals wherever possible.
    > >
    > > Thanks,
    > > Allan.
    > > --
    > > Allan Herriman
    > > Advanced Networks Division    +61 3 9210 5527 Tel
    > > Agilent Technologies, Inc.    +61 3 9210 5550 Fax
    > > 347 Burwood Highway  Forest Hill 3131 Australia
    > >
    > > 
    >
    >
    >
    >___________________________________
    >Webmail Nerim, http://www.nerim.net/
    >
    >
    >
    
    
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    Follow upAuthor
    Re: [oc] Async reset: active high or active low?Niclas Hedhman
    Re: [oc] Async reset: active high or active low?Rudolf Usselmann

     
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