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From: kokloon@h...
Date: Wed, 16 Apr 2003 09:54:10 -0100
Subject: [oc] How to model capacitor in Verilog??

Hi all,

I am trying to model a capacitor using standard Verilog, but 
I have no idea how to do it...

Does anybody have any idea on this??
Issit like this??

trireg (large) #(0,1,9) capacitor

Thanks,
Kok Loon