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Message
From: "Ho, Wen Jei x4297" <who1@r...>
Date: Sun, 26 Jan 2003 08:17:28 -0800
Subject: RE: Re: [oc] Real newbie questions
Some people even use board level schematic net list as testbench.
Wen
-----Original Message-----
From: owner-cores@o...@ROCKWELLCOLLINS On Behalf Of
John Sheahan <jrsheahan@o...>
Sent: Saturday, January 25, 2003 3:10 PM
To: cores@o...
Subject: Re: Re: [oc] Real newbie questions
On Sat, Jan 25, 2003 at 02:35:46PM -0000, tanveer tan
wrote:
> !!! r there any syntheesizable testbenches??
>
>
> tanveer
Sure.
I worked with quickturn emulators a while back.
These are either arrays of FPGA's with software to spread
out the design, or arrays of dedicated special tiny CPUs.
They are there to simulate a big design fast.
(close to real time)
Here, the simulator running the testbench is the bottleneck.
Using a synthesizeable testbench, together with RAM is one
solution.
Its perhaps possible to argue an IC tester is another
example.
john
application/ms-tnef
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