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Message
From: "tanveer tan" <tanveer008@r...>
Date: 25 Jan 2003 14:35:46 -0000
Subject: Re: Re: [oc] Real newbie questions
On Tue, 21 Jan 2003 Rudolf Usselmann wrote :
>On Tue, 2003-01-21 at 17:17, Lars Segerlund wrote:
> >
> > Now, VHDL/Verilog AHPL and so on is actually very good for
>programing,
> > the programed design is indispensible for the verification of
>the
> > circuit. Also this 'programmed' model can be a good base to
>start the
> > hardware abstraction from, since it is easier to do a
>'stepwise
> > refinement' of the choosen design and perhaps some redesing
>during the
> > HW description phase.
>
>Lets not confuse what we are talking about: You do not program
>when you are designing a circuit. You are describing the
>behavior
>of the circuit.
>
>Sometimes, people use a style similar to conventional
>programming
>languages to write a test bench. These test benches might have
>a
>lot of sequential code. This is however very seldom
>synthesizable
>code.
!!! r there any syntheesizable testbenches??
tanveer
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