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Message
From: Niclas Hedhman <niclas@h...>
Date: Wed, 22 Jan 2003 10:24:58 +0800
Subject: Re: [oc] 8051 VHDL models search
On Wednesday 22 January 2003 11:10, winn70@m... wrote:
> > hello,
> > where can i download examples source code of assembly for 8051 to
>
> control analog devices.And I like to read programming books for MCS51.
>
> I will be happy for your information.
I designed an RTOS and bytecode interpreter in 8031 (8051 with ROM) ASM about
18 years ago, and the only book I ever read was the Databook coming from
Intel itself. It should be available as a download from Intel's web site, if
not the whole book, at least the full datasheet, which is the essence of what
you need (provided you know assembly for other CPUs).
"to control analog devices" is also an extremely broad term. You have a
pleflora of access types, parallel, SPI, CAN, I2C and so forth, and (except
for parallel) you should have hardware support in your VHDL design for the
interface(s) of your choice, or the CPU will be very busy receiving bits and
not much else.
I also have a bit of a problem why you want to go for a 8051 design in VHDL,
when there are so many other, much better CPU architectures out there. Even
Z80, IMHO, is a lot easier to program than the notoriously cumbersome, slow
and memory wasting;
mov b, COUNT
mov r7, HIGH( DEST_ADDR )
mov r6, LOW( DEST_ADDR )
mov r5, HIGH( SRC_ADDR )
mov r4, LOW( SRC_ADDR )
LOOP:
mov dph, r5
mov dpl, r4
movx a,@dptr
inc dptr
mov r5, dph
mov r4, dpl
mov dph, r7
mov dpl, r6
movx @dptr,a
inc dptr
mov r7, dph
mov r6, dpl
djnz b, LOOP
to copy external memory from one place to another.
If I recall correctly (have not done much in this CPU) Z80 does the loop in a
single line, well, the 8088 does.
The main reason for choosing the 8031 and its siblings in those days was its
peripherals (for us the 187kbps hardware address detection UART) and very
competitive price. This hardly doesn't apply anymore.
Anecdote; Intel 8031 with a Copyright mark of 1980 (not 1982) has an
interesting bug when operating the UART in Mode 1 (perhaps the others) that
if both a UART and a Timer interrupt happens in the same instruction cycle,
it will spawn to both interrupt routines but loose one return address.
According to Intel, that was never the case, even though we could prove it,
and the 1982 edition had it rectified. It nearly bankrupt the company, in
fact the CEO had already made the decision to shut the company down, when one
of my colleagues suggested to try a new shipment of CPUs.
MicroChip PIC16X73 (other?) anno 1996/97 had a similar bug, where the GIE
(Global Interrupt Enable) is not cleared for the second interrupt if two
happens in the same instruction cycle. The difference is that MicroChip
acknowledged the fact, and thanked me in writing to have noticed and reported
it (incl a work around), and gave me very good pricing on low quantity
purchases thereafter.
Tell-tale of attitude between companies.
Niclas
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