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Message
From: Niclas Hedhman <niclas@h...>
Date: Tue, 21 Jan 2003 09:20:55 +0800
Subject: Re: [oc] Real newbie questions
Well, since I am a programmer @ profession, it shouldn't be a problem to learn
VHDL, should it...
As John said, "It takes some head rearrangement.", but I have done that
before, assembly -> basic -> procedural -> OO.
Any good literature to recommend?
Niclas
On Monday 20 January 2003 20:36, Joachim Strömbergson wrote:
> Aloha!
>
> John Sheahan wrote:
> > verilog is cleaner and more concise for me. But this is a religious
> > issue. Yes - RTL is different to schematic. It takes some head
> > rearrangement. But its time well spent.
> > Compare a 32 bit adder in schematic and rtl and tell me which is more
> > obvious. Or a state machine. Than change the adder to 48 bits..
> > I suspect schematic adherents for digital design are now few and far
> > between - particularly in those doing any regular not-tiny design.
> > The which-language wars are very much ongoing though :)
>
> I agree with this. There are still quite a few people using schematic
> design entry for digital design. CPLD, FPGA and ASIC designs. The
> schematics are always using hierarchies which allows you to contain/enclose
> the functional details in boxes and thereby abstract away all irrelevant
> details on higher levels.
>
> Esp people that are concerned to get absolutely minimal designs/maximum
> performance seem to use schematic design entry. The comparison between
> machine language/assembler vs high level languages are obvious.
>
> If I remember correctly Ray Andraka of CORDIC in FPGA fame uses schematic
> entry with great results. (BTW: are you on this list Ray?). This makes good
> sense esp in fixed architectures like LUT based FPGAs where schematic entry
> allows you to do the mapping onto the resources by hand.
>
> If you look at the Altera Quartus-II tools, it actually uses schematic
> entry at least for interconnect, but you can instansiate gates directly
> too.
>
> There are also several tools on the market that uses schematic, table, flow
> charts, state bubbles and interconnect graphical descriptions as a
> representation. These tools generate HDL (Verilog or VHDL) on RTL-level, or
> black box GTL.
>
> Personally, I think flow charts are evil, have a general distrust in the
> proclaimed productivity gained compared to design entry using paper &
> pencil, whiteboard and a good editor with syntax aware modes. (Emacs is a
> great example.)
>
> Use the graphical tools for interconnect on a higher level, and possibly
> schematic entry for those blocks where it is absolutely necessary to have
> 100% control of what gates are used in specific bloks. Use straight RTL for
> the rest.
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