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Message
From: John Sheahan <jrsheahan@o...>
Date: Sun, 19 Jan 2003 19:28:31 +1100
Subject: Re: [oc] Real newbie questions
On Sat, Jan 18, 2003 at 12:02:46PM +0800, Niclas Hedhman wrote:
> I recently got Protel DXP, and it gives me the impression I can design
> FPGA/CPLD in schematic capturing, and have it output VHDL to make the
> FPGA/CPLD.
> Question;
> 1. Is this actually so?
a flow from schematic to vhdl to fpga would make little sense.
In a schematic - you have to instantiate paricular devies - chosen
from a library. What library did you use? thats the device you have
targetted. Perhaps there are several sized members availave.
ypu my be able to get a structural gate vhdl netlist out - thats
exuivilant to disassembling compiled code. May be useful for debug
- but not very useful to port to a new architecture.
Write VHDL or Verilog RTL with any decent editor (with support for the
language) Synthesize with the free (beer) tools from Xilinx or Altera.
I don't think schematic capture for fpga is of much relevance any more.
Those tools will also allow you to fit the design into any of the
ranges of parts they make. 192 bits of fifo is tiny - will go into
most any fpga and some cpld's. (unless you are doing horrible
clocking)
john
> 2. How would I know how much can be crammed into a given FPGA?
>
> In particular, I need (and drew that as schematics) a asynchronous 1-bit wide
> and 192bit deep FIFO-like circuit. Ironically, only 6pins + power is
> required. How do I go about selecting a device?
>
> Sorry for being "un-educated", but OSS is typically rather "understanding",
> and I hope OSH is the same. Any help is greatly appreciated.
>
> Niclas Hedhman
>
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