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Message
From: paydaran_parsa_co@y...
Date: Tue, 31 Dec 2002 05:49:47 -0100
Subject: Re: [oc] Fwd: UART CORE . I need the xilix uart core with fifo
----- Original Message -----
From: Jamil Khatib <jamilkhatib75@y... >
To: cores@o...
Date: Tue, 21 Nov 2000 02:07:14 -0800 (PST)
Subject: [oc] Fwd: New book on front-end design processes by
example
>
>
> Check this book. The Aithor is an OpenCores and
> OpenTech cdrom supporter
>
> Regards
> Jamil Khatib
>
> --- VhdlCohen@a... wrote:
> > From: VhdlCohen@a...
> > Date: Fri, 17 Nov 2000 22:16:23 EST
> > Subject: New book on front-end design processes by
> > example
> > To: khatib@i...
> >
> > --
> > The book "Component Design by Example ... a
> > Step-by-Step Process Using VHDL
> > with UART as Vehicle", ISBN 0-9705394-0-1 was just
> > released, and your
> > project
> > may benefit from it regardless of which HDL you use.
> >
> >
> > This book uses a full featured UART with FIFO as a
> > design
> > vehicle to demonstrate the front-end design
> > processes including:
> > . Requirement Specification . Design
> > Verification
> > . Architectural Plan . Documentation &
> > Delivery
> > . Verification Plan . Design
> > Integration
> > . Design and Synthesis . Process
> > Guidelines
> >
> > It provides methodologies generally accepted and
> > recommended in many
> > textbooks,
> > including: "Reuse Methodology Manual", "Writing
> > Testbenches",
> > "Functional verification of HDL Models",
> > "Verification Methodology
> > Manual for Code Coverage in HDL Designs", and "VHDL
> > Coding Styles and
> > Methodologies".
> >
> > This book provides helpful guides and templates for
> > all front-end phases of a
> > design,
> > most of which are independent of the HDL
> > implementation or verification
> > languages.
> > It demonstrates a reusable transaction-based
> > verification methodology using
> > TextIO command files with a small instruction set
> > that includes callable
> > TextIO
> > command subroutines.
> >
> > CD Includes:
> > Advanced Design of Parameterized UART with
> > Subblocks, FIFO Buffering, and
> > Interrupt Controller. Advanced Testbench Code with
> > Client/Server Object
> > Oriented Style, and Text Command Files. Reusable
> > TextIO Parser Package,
> > Design of Verifier with Error Detection and
> > Transaction Logging EMACS Editor
> > with Tshell for Windows NT, 9X, Standard VHDL
> > Packages, VHDL Syntax and
> > Syntax Help.
> >
> > From pre-publication review:
> > " ... provides specific guidelines and examples for
> > architectural definition
> > and requirements generation, to hierarchical
> > partitioning, and detailed
> > coding standards for design reuse, through testbench
> > verification strategies
> > useful for todays' complex designs."
> >
> > From foreword:
> > " ... goes beyond just the implementation phases of
> > design, and takes
> > on the procedures from conception to specification
> > and planning.
> > PLEASE DON'T DISMISS THESE SECTIONS! useful to any
> > designer
> > or design team. I expect it will be the foundation
> > for a future filled
> > with IP. Read this before your next project. Then
> > reread it afterward.
> > You will benefit both times."
> >
> > For more information, foreword, preface, TOC, and
> > disk see:
> > http://www.vhdlcohen.com/
> >
> > Ben Cohen VhdlCohen@a...
> > Publisher, Trainer, Consultant
> > Author of:
> > . Component Design by Example, 2001 isbn
> > 0-9705394-0-1
> > . VHDL Coding Styles and Methodologies, 1999 isbn
> > 0-7923-8474-1
> > . VHDL Answers Frequently Asked Questions, 1998
> > isbn 0-7923-8115-7
> >
> >
>
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