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From: Agador Sparticus <mega_gojira@w...>
Date: Mon, 28 Jan 2002 13:06:51 -0800 (PST)
Subject: Re: [oc] Visual VHDL.

What about netlists?

--- Jean Masson <Jean.Masson@l...> wrote:
>I know that graphic is an antinomic concept in VHDL. Meanwhile, a form of graphic components, wich
>are inside
>cores of Visual C++, C++ Builder or Delphi, should be useful in a VHDL context. FPGA Express has
>this sort of idea in his
>entity wizard, where you obtain an entity as a result of graphical definitions of signals. I wish a
>sort of integration of VHDL GUI
>in current development systems, a CASE graphical tool in parallel with a textual language. A
>graphical expression of top-down
>hierarchy should prevent errors, or confusions, in names of signals in complex projects.



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