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Frequently Asked Questions
3 Design Guidelines
3.1 What design language do you use?
There is no preferred language and each designer uses their language of choice. Keep in mind that a core written in a seldom used language will not be very useful. Most designers use either VHDL or Verilog.
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3.2 What is the preferred System-On-A-Chip (SoC) bus for opencores?
The preferred bus is WISHBONE. This is the only commonly used SoC bus which is truly free. Rudolf Usselmann has analysed the advantages of the common SoC busses. His report is available at Wishbone page.
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3.3 Does OpenCores have any coding and interface guidelines?
The OpenCores coding guidelines are available in CVS
Also have a look at some of the compliant cores, such as the 'wishbone' cores under Browse :: Projects menu.
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