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Most popular projects We use a few icons to help identify projects: Indicates new project, that has been added in the last 30 days. Indicates project that is ready to use Indicates a WISHBONE Compliant Core VLM = Visits Last Month (how many people accessed project) OpenRISC 1000   Updated on: 09-Jun-2008   VLM: 11588 OpenRISC 1000 is an architecture of a family of open source, synthesizable RISC microprocessor cores. It is a 32-bit load and store RISC architecture designed with emphasis on speed, compact instruction set and scalability. OpenRISC 1000 targets ...   Category :: Microprocessor Language :: Verilog License :: LGPL Phaze :: ASIC proven Standard :: Wishbone compliant core Development status :: Production/Stable   Ethernet MAC 10/100 Mbps   Updated on: 24-Sep-2007   VLM: 6270 The Ethernet MAC (Media Access Control), sublevel within the Data Link Layer of the OSI reference model. This core is designed for implementation of CSMA/CD LAN in accordance with the IEEE 802.3 standards. The MAC is the portion of ethernet core ...   Category :: Communication controller Standard :: Wishbone compliant core Development status :: Production/Stable   USB 1.1 Host and Function IP core   Updated on: 22-Mar-2008   VLM: 5907 USB 1.1 host and function modes of operation. Full (12Mbps) and low speed (1.5Mbps) operation. Isochronous data transfers supported. Function mode supports four endpoints.   Category :: Communication controller Language :: Verilog License :: LGPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   I2C controller core   Updated on: 09-Apr-2008   VLM: 4324 I2C is a two-wire, bidirectional serials bus that provide a simple, efficient method of data exchange between devices.   Category :: Communication controller Language :: Verilog Language :: VHDL Phaze :: ASIC proven Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   ZPU - the worlds smallest 32 bit CPU with GCC toolchain   Updated on: 25-Jun-2008   VLM: 3896 This is the worlds smallest 32 bit CPU with a GCC/GDB toolchain, operating systems support(eCos), simulator, etc. Multiple VHDL implementations available. BSD license, except for those pieces to the puzzle that already have another open so...   Category :: Microprocessor Language :: VHDL Phaze :: Design done Phaze :: FPGA proven Phaze :: Specification done Standard :: Wishbone compliant core Development status :: Beta Development status :: Production/Stable   a VHDL 16550 UART core   Updated on: 18-Jun-2008   VLM: 3131 a 16550 compatible UART in VHDL   Category :: Communication controller Dependencies :: Other cores Language :: VHDL Phaze :: Design done Development status :: Production/Stable   JOP: a Java Optimized Processor   Updated on: 04-Jul-2008   VLM: 2435 JOP is the implementation of the Java Virtual Machine (JVM) as concrete machine in hardware. The design is full synthesizable and fits in low-cost FPGA devices from Altera and Xilinx.   Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   CAN Protocol Controller   Updated on: 30-Apr-2008   VLM: 2051 CAN (Controller Area Network) is a widely used control network protocol. Typical Apllications are automation and in-car networking. The project aims to develop an open source implementation of CAN Protcol Version 2.0 Part A and B. It should be...   Category :: Communication controller Standard :: Wishbone compliant core Development status :: Production/Stable   Plasma - most MIPS I(TM) opcodes   Updated on: 05-Jul-2008   VLM: 2012 The Plasma CPU core supports interrupts and all MIPS I(TM) user mode instructions except unaligned load and store operations (which are patented) and exceptions.   Category :: Microprocessor Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable   WISHBONE Builder   Updated on: 09-Jun-2008   VLM: 1863 A WISHBONE interconnect matrix generator written in PERL/Tk. Generates HDL from a text description or via GUI input.   Category :: SoC Language :: Verilog Language :: VHDL Standard :: Wishbone compliant core Development status :: Production/Stable   Perlilog   Updated on: 06-Mar-2004   VLM: 1858 Perlilog is a design tool, whose main target is easy integration of Verilog IP cores for System-on-Chip (SoC) designs. It's also a good starting point for writing scripts which handle Verilog code in general   Category :: Other Development status :: Beta   aeMB   Updated on: 01-Jul-2008   VLM: 1840 A clean room implementation of an EDK3.2 binary compatible Microblaze processor core. It is FPGA proven and has been extensively simulated using Icarus Verilog 0.8.5 and GPLCVER 2.11a to confirm performance. Simulation code is compiled using GCC ...   Category :: Microprocessor Language :: Verilog License :: LGPL Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Beta Development status :: Production/Stable   VGA/LCD Controller   Updated on: 13-May-2004   VLM: 1807 The OpenCores VGA/LCD Controller core is a WISHBONE rev.B3 compliant embedded VGA core capable of driving CRT and LCD displays.   Category :: Video controller Language :: Verilog Phaze :: ASIC proven Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   HiCoVec - a configurable SIMD CPU   Updated on: 06-Jun-2008   VLM: 1794 The HiCoVec processor is based on a simple 32 bit scalar unit and connected with a vector unit for SIMD operations. The amount of data simultaneously processed in the vector unit can be configured as well as the amount of vector registers to h...   Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Beta   Ethernet 10GE MAC   Updated on: 07-Jun-2008   VLM: 1792 The 10GE MAC implements the MAC layer for 10Gbps operation as defined in 802.3ae. The MAC is designed to be compact while providing the necessary functionally to be compliant.   Category :: Communication controller Language :: SystemC Language :: Verilog License :: LGPL Standard :: Wishbone compliant core Development status :: Beta