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Last updated projects We use a few icons to help identify projects: Indicates new project, that has been added in the last 30 days. Indicates project that is ready to use Indicates a WISHBONE Compliant Core VLM = Visits Last Month (how many people accessed project) ClaiRISC - runs 12bit opcode PIC family.   Updated on: 22-Nov-2008   VLM: 225 This is another RISC core which is compatible with the 12 bit opcode PIC family.   Category :: Microprocessor Language :: Verilog Phaze :: Design done Phaze :: FPGA proven Development status :: Production/Stable   Plasma - most MIPS I(TM) opcodes   Updated on: 21-Nov-2008   VLM: 2406 The Plasma CPU core supports interrupts and all MIPS I(TM) user mode instructions except unaligned load and store operations.   Category :: Microprocessor Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable   Functional simulation models for commercially available RAMs   Updated on: 18-Nov-2008   VLM: 168 The simu_mem project provides functional simulation models of commercially available RAMs. The following types are presently supported: - asynchronous static SRAMs - synchronous static RAMs ("Zero Bus Turnaround" RAM, ZBT RAM) ...   Category :: Memory core Language :: VHDL License :: LGPL Phaze :: Design done Development status :: Beta   OpenRisc Development Board   Updated on: 18-Nov-2008   VLM: 641 Opensource OpenRisc Development Board. All CADsoft Eagle design files available to recreate the board using EagleLite, a freeware PCB design tool. Uses the largest Cyclone 2 device available in a QFP package, thus allowing larger RTL designs to b...   Category :: Prototype board Development status :: Production/Stable   Cache: Cache Architecture for Configurable Hardware Engine   Updated on: 18-Nov-2008   VLM: 438 The Cache, cache architecture for configurable hardware engine is a flexible and reconfigurable processor. Traditional microprocessors take lots of complex background logic circuit that work for improving IPC (instructions per cycle). the complex...     JOP: a Java Optimized Processor   Updated on: 17-Nov-2008   VLM: 1370 JOP is the implementation of the Java Virtual Machine (JVM) as concrete machine in hardware. The design is full synthesizable and fits in low-cost FPGA devices from Altera and Xilinx.   Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   Fix-Point Cordic Engine   Updated on: 17-Nov-2008   VLM: 130 Feature: 1. Vector Rotation – Conversion of Polar Coordinates to Rectangular Coordinates 2. Vector Translation – Conversion of Rectangular Coordinates to Polar Coordinates 3. Sine and Cosine calculation Application: 1. NCO, DDS 2. DDC, ...     USB 1.1 Host and Function IP core   Updated on: 17-Nov-2008   VLM: 2767 USB 1.1 host and function modes of operation. Full (12Mbps) and low speed (1.5Mbps) operation. Isochronous data transfers supported. Function mode supports four endpoints.   Category :: Communication controller Language :: Verilog License :: LGPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   OpenRISC 1000   Updated on: 16-Nov-2008   VLM: 12200 OpenRISC 1000 is an architecture of a family of open source, synthesizable RISC microprocessor cores. It is a 32-bit load and store RISC architecture designed with emphasis on speed, compact instruction set and scalability. OpenRISC 1000 targets ...   Category :: Microprocessor Language :: Verilog License :: LGPL Phaze :: ASIC proven Standard :: Wishbone compliant core Development status :: Production/Stable   BU PACMAN   Updated on: 15-Nov-2008   VLM: 260 A pacman game implemented on Spartan3 dev board by digilent. As the final project of EC551 - Advanced Digital Design using Verilog from Boston University.   Category :: Other Language :: Verilog License :: GPL Phaze :: Specification done Development status :: Alpha   Zet - The x86 (IA-32) open implementation   Updated on: 14-Nov-2008   VLM: 1587 This project implements a version of the common Intel IA-32 instruction set into a commercial FPGA.   Category :: Microprocessor Language :: Verilog License :: GPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Alpha   ZPU - the worlds smallest 32 bit CPU with GCC toolchain   Updated on: 12-Nov-2008   VLM: 2780 This is the worlds smallest 32 bit CPU with a GCC/GDB toolchain, operating systems support(eCos), simulator, etc. Multiple VHDL implementations available. BSD license, except for those pieces to the puzzle that already have another open so...   Category :: Microprocessor Language :: VHDL Phaze :: Design done Phaze :: FPGA proven Phaze :: Specification done Standard :: Wishbone compliant core Development status :: Beta Development status :: Production/Stable   S1 Core   Updated on: 12-Nov-2008   VLM: 531 The S1 Core is a reduced version of the OpenSPARC T1 released by Sun Microsystems. While the T1 is a complete microprocessor with 8 cores (capable of running up to 32 concurrent threads) and includes a crossbar switch, L2 Caches and several other...   Category :: Microprocessor Language :: Verilog License :: GPL Phaze :: Design done Standard :: Wishbone compliant core Development status :: Production/Stable   CAN Protocol Controller   Updated on: 12-Nov-2008   VLM: 1974 CAN (Controller Area Network) is a widely used control network protocol. Typical Apllications are automation and in-car networking. The project aims to develop an open source implementation of CAN Protcol Version 2.0 Part A and B. It should be...   Category :: Communication controller Standard :: Wishbone compliant core Development status :: Production/Stable