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Last created projects We use a few icons to help identify projects: Indicates new project, that has been added in the last 30 days. Indicates project that is ready to use Indicates a WISHBONE Compliant Core VLM = Visits Last Month (how many people accessed project) AES   Updated on: unknown   VLM: 5 I want to make a AES project, there is something problem, if you can help me ,give me a hand     68000 Compatible CPU core   Updated on: unknown   VLM: 34 A FPGA based CPU core compatible (timing as well as ISA) with MC68000. Although there are a couple of open source 68k cores are available on the net, but they lack design documentation and hence it is very difficult to comprehend them. I aim t...     Bluespec MD6   Updated on: unknown   VLM: 10 The first hardware implementation, a novel hashing algorithm by Ron Rivest. This algorithm is highly parallel. This code has been proven on the XUP platform, on which hashing speeds of 233 MB/s have been achieved.     Scalable Arbiter   Updated on: 08-Aug-2008   VLM: 327 A scalable synchronous round-robin arbiter. The arbiter is designed to run at reasonable clock speeds with up to hundreds of request lines, and it grants in just a few clock cycles. The arbiter's interface has individual request and grant lines f...   Category :: Other Language :: Verilog Development status :: Beta   Standard SDIO Host Controller with Wishbone Interface   Updated on: 04-Aug-2008   VLM: 135 Standard SDIO Host Controller with Wishbone interface.     a VHDL 8254 Timer   Updated on: 16-Aug-2008   VLM: 541 a VHDL timer, based upon the Intel 8254   Category :: Other Dependencies :: Other cores Language :: VHDL Development status :: Beta   Kotku - The IBM PC complete system   Updated on: 03-Aug-2008   VLM: 237 This project is connected with Zet, the FPGA port of the IA-32 processor.     Asynchronous WISHBONE-compatible SDRAM controller   Updated on: 02-Aug-2008   VLM: 126 Yet Another Dynamic Memory Controller... after various pleagues with DRAM controllers, I decided to write my own. This one is hardware-proven on the OMRP.     CCIR656 Video Capture Interface   Updated on: unknown   VLM: 14 Design a CCIR656 video capture interface module. The module has wishbone bus. The video data will be buffered and transfered to main memory by DMA.     sdram control core   Updated on: 31-Jul-2008   VLM: 127 read and write sdram chip,can config for any sdram chip.