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Development status :: Mature We use a few icons to help identify projects: Indicates new project, that has been added in the last 30 days. Indicates project that is ready to use Indicates a WISHBONE Compliant Core VLM = Visits Last Month (how many people accessed project) ACEX 1K50 board   Updated on: 11-Sep-2004   VLM: 223 A prototyping board with ACEX 1K50, 128 KB SRAM, 512 KB Flash, serial driver and wtachdog.   Category :: Prototype board License :: GPL Phaze :: FPGA proven Development status :: Mature Development status :: Production/Stable   AHB to Wishbone Bridge   Updated on: 07-Sep-2007   VLM: 357 Converts AHB protocol to Wishbone protocol for interfacing two SoC's (AHB Master and Wishbone Slave).   Category :: SoC Language :: Verilog Phaze :: Design done Phaze :: FPGA proven Phaze :: Specification done Standard :: Wishbone compliant core Development status :: Mature   EPP v1.9   Updated on: 27-Apr-2003   VLM: 134 well It will be a simple EPP interface from a prepherial point of view , and will be a FSM based synchronous design in verilog.   Category :: Communication controller Development status :: Mature   I2C Traffic Logger   Updated on: 10-May-2004   VLM: 187 An I2C 2 wire serial bus logger designed on Verilog synthesized code captures I2C transections into an external memory. The size of the transection captured is limited by the size of the external memory. I2C traffic logger is an essential di...   Category :: Communication controller Development status :: Mature   MCPU - A minimal CPU for a CPLD   Updated on: 29-Jul-2008   VLM: 858 mcpu is a minimal cpu designed to fit into a 32 macrocell CPLD. 4 Instructions and access to 64 bytes of memory are supported. Sourcecode is provided in VHDL and Verilog and occupies only a single printed page.   Category :: Microprocessor Language :: Verilog Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Mature Development status :: Production/Stable   nnARM core   Updated on: 15-Oct-2001   VLM: 694 ARM-7 clone   Category :: Microprocessor Standard :: Wishbone compliant core Development status :: Mature   OPB-compatible OneWire Master   Updated on: 09-Oct-2007   VLM: 148 This is a OneWire Master core that is fully compatible with the Xilinx OPB specification.   Category :: Communication controller Language :: Verilog License :: GPL Phaze :: Design done Phaze :: FPGA proven Development status :: Mature Development status :: Production/Stable   PCI Board   Updated on: 20-Dec-2005   VLM: 437 A versatile small pci board project based on Spartan-II.   Category :: Prototype board License :: GPL Phaze :: Design done Development status :: Mature   Serial Uart   Updated on: 21-Jan-2003   VLM: 474 An other version of a tiny Uart. designed to fit in a small FPGA.   Category :: Communication controller Standard :: Wishbone compliant core Development status :: Mature   tiny8   Updated on: 11-Feb-2007   VLM: 417 TINY8 an 8 microprocessor with assembler. Very simple for educational use. AHDL/Schematic with MAX+plus II 10.0 BASELINE device: ALTERA EPF10K10LC84-4   Category :: Microprocessor Language :: VHDL Development status :: Mature   TV80   Updated on: 24-Mar-2006   VLM: 431 The TV80 is a synthesizable 8-bit Z80-compatible microprocessor. It is a Verilog port of Daniel Wallner's T80, with some optimizations and a new verification environment. Documentation available on the web at http://ghutchis.googlepages.com/t...   Category :: Microprocessor Language :: Verilog Phaze :: ASIC proven Phaze :: FPGA proven Development status :: Mature Development status :: Production/Stable