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Development status :: Alpha We use a few icons to help identify projects: Indicates new project, that has been added in the last 30 days. Indicates project that is ready to use Indicates a WISHBONE Compliant Core VLM = Visits Last Month (how many people accessed project) 1-bit Microprocessor   Updated on: 17-Oct-2006   VLM: 456 This project, in VHDL, implements a single-bit microprocessor based on the now obsolete Motorola MC14500B Industrial Control Unit. The ICU is basically a logic sequencer with a 4-bit instruction unit (16-instructions). In addition to the ICU, t...   Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: Design done Development status :: Alpha   10G Ethernet MAC   Updated on: 10-Apr-2008   VLM: 437 The 10G ethernet mac core. It is compliant with ieee 802.3ae. Transmit engine and Receive engine have been finished.   Category :: Communication controller Language :: Verilog Development status :: Alpha   8-bit microcontroller with extended peripheral set   Updated on: 10-Aug-2008   VLM: 258 The goal of this project is to create a very well documented, fully synthesizable VHDL model of an 8-bit microcontroller with extended peripheral set. The model should be highly configurable, making it possible to exclude unused peripheral units....   Category :: Microprocessor Language :: VHDL License :: LGPL Development status :: Alpha   8051 core   Updated on: 29-Jul-2008   VLM: 1599 The basic form of 8051 core includes several on-chip peripherals, like timers and counters, additionally there are 128 bytes of on-chip data memory and up to 64K bytes of on-chip program memory.   Category :: Microprocessor Standard :: Wishbone compliant core Development status :: Alpha   adat receiver   Updated on: 25-Jul-2008   VLM: 143 This is a feed forward receiver for an 8 channel ADAT lightpipe optical audio datastream. It outputs the audio data on a data bus, user databits on seperate pins, each updated every ADAT frame. It also outputs the recovered wordclock on a pin. ...   Category :: Communication controller Language :: VHDL Development status :: Alpha   Bluetooth baseband controller   Updated on: 16-Mar-2002   VLM: 367 The Bluetooth is a standard protocol for wireless connection between devices such as cell phones, PDAs, PCs and any other device.   Category :: Communication controller Standard :: Wishbone compliant core Development status :: Alpha   Confluence OpenRisc 1000   Updated on: 17-Jun-2004   VLM: 128 This is a Confluence implementation of the OpenRisc 1000 architecture.   Category :: Microprocessor Language :: Other Development status :: Alpha   DEFLATE   Updated on: 05-Jun-2006   VLM: 71 The deflate is a VHDL implementation of the popular DEFLATE algorithm for data compression. More information on DEFLATE and its implementation are available at the zlib home page http://www.zlib.net/zlib_docs.html   Language :: VHDL License :: GPL Phaze :: Design done Standard :: Wishbone compliant core Development status :: Alpha   embedded z8 µController core   Updated on: 15-Mar-2007   VLM: 136 The Z8 family from Zilog represents a flexible 8 bit microcontroller architecture, which are suitable for embedded applications.   Category :: Microprocessor Development status :: Alpha   External parallel port to internal wishbone master interface   Updated on: 26-Jun-2008   VLM: 138 This core is intended to be used as an interface between some functionality in an FPGA and an external microcontroller. The external microcontroller provides a simple 8bit interface to control some functions within the FPGA. These functions ar...   Category :: System controller Language :: VHDL License :: GPL Phaze :: Specification done Development status :: Alpha   High Speed SDRAM Controller With Adaptive Bank Management and Command Pipeline   Updated on: 23-Aug-2008   VLM: 566 HSSDRC is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. The main features of HSSDRC IP core are: 1. Adaptive SDRAM bank control : command sequence is depending upon previous accesses to...   Category :: Memory core Language :: Other Phaze :: Design done Development status :: Alpha Development status :: Production/Stable   Lightweight 8080 compatible core   Updated on: 19-Aug-2008   VLM: 203 Small, microprogrammed 8080-compatible cpu core. Emphasis on area reduction and design simplicity.   Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Alpha   Macroblock Motion Detection   Updated on: 16-Dec-2004   VLM: 43 Motion detection for macroblocks in image frames   Language :: Verilog Development status :: Alpha   MicroRISC II   Updated on: 01-Apr-2002   VLM: 266 5 Stage Pipeline RISC Core for embedded control of devices. Optimized for the SpartanII and Virtex line of FPGA's.   Category :: Microprocessor Development status :: Alpha   Mini AES   Updated on: 28-Dec-2005   VLM: 236 Advanced Encryption Standard (AES) implementation with small area/resources utilization.   Category :: Crypto core Language :: VHDL Phaze :: Design done Development status :: Alpha   MP3 decoder   Updated on: 05-Jul-2005   VLM: 565 This project is to implement an MP3 decoder in VHDL without a processor core. Right now, three main modules of MP3 decoding process have been accomplished:Huffman decoder, IMDCT and Filterbank. These components are written in VDHL and the funct...   Category :: SoC Development status :: Alpha   nCore   Updated on: 28-Oct-2007   VLM: 171 This is a little-little processor core. It has 16 instructions. It is under developement again, since the latest version is deleted... It is not yet verified, tested, etc. but it's ready to compile.   Category :: Microprocessor Language :: Verilog License :: GPL Development status :: Alpha   oks8   Updated on: 24-Jan-2006   VLM: 174 oks8 is intended to provide a microcontroller in Verilog that like the KS86C4204/C4208/P4208 microcontroller (Samsung Inc.).   Category :: Microprocessor Language :: Verilog License :: GPL Standard :: Wishbone compliant core Development status :: Alpha   OpenFire Processor Core   Updated on: 13-Dec-2007   VLM: 212 The OpenFire soft processor is an open source Verilog implementation of the Xilinx MicroBlaze processor. Like the MicroBlaze, the OpenFire is a 32-bit RISC processor based on the DLX architecture by Hennessy and Patterson. The OpenFire processor...   Category :: Microprocessor Language :: Verilog Phaze :: FPGA proven Development status :: Alpha   pAVR   Updated on: 22-Aug-2006   VLM: 434 pAVR (pipelined AVR) is an 8 bit RISC controller, compatible with Atmel's AVR core, but about 3x faster in terms of both clock frequency and MIPS. It achieves this performance by using a deep pipeline (with 6 stages).   Category :: Microprocessor Development status :: Alpha   SardMIPS   Updated on: 09-Feb-2006   VLM: 224 It's a synthesizable parametric IP core of 32 bit RISC processor supporting full MIPS R2000 ISA, by using SystemC HDL. An optional CP0 coprocessor implementing full exception handling was also modelled. Also 64 bit pipeline multiplier supporting ...   Category :: Microprocessor Category :: SoC Language :: Other License :: GPL Development status :: Alpha   scsi_chip   Updated on: 01-Oct-2008   VLM: 294 this is a interface between SCSI and 32 bit procesor, with other features, first proyect   Category :: System controller Language :: Verilog Development status :: Alpha   SHA1 Secure Hash Algorithm   Updated on: 08-Jul-2004   VLM: 213 Verilog Implementation of SHA1 Secure Hash Algorithm   Category :: Crypto core Development status :: Alpha   Simple All Digital FM Receiver   Updated on: 26-Oct-2006   VLM: 369 The design of the All Digital FM Receiver circuit in this project uses Phase Locked Loop (PLL) as the main core. The task of the PLL is to maintain coherence between the input (modulated) signal frequency, and the respective output frequency, via...   Category :: Other Language :: VHDL License :: GPL Phaze :: Design done Phaze :: FPGA proven Development status :: Alpha   Simple-CPU SC91-A   Updated on: 07-Oct-2005   VLM: 124 Simple CPU is an open source 32 bits RISC processor based on a load / store architecture written in VHDL. As target, developpement suite will support GCC. Simulator and assembly compilers will be available in Java. Simple CPU is actually impleme...   Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: Specification done Development status :: Alpha   simpleUart -   Updated on: 13-Apr-2006   VLM: 40 This is a simple yet powerful uart core written in Verilog. It contains a harmonic frequency synthesizer for a baud rate generator (effectively a clock multiplier) so it can use just about any clock frequency. It's fairly small (about 83 slices).   Language :: Verilog Development status :: Alpha   SpaceWire   Updated on: 10-Jul-2005   VLM: 255 "In short, SpaceWire (SpW)is a Network for space applications composed of nodes and routers interconnected through bi-directional high-speed digital serial links." A communication system for interconnecting a plurality of individual units whic...   Category :: Communication controller Language :: Verilog Standard :: Wishbone compliant core Development status :: Alpha   Synchronous-DRAM Controller   Updated on: 15-Oct-2001   VLM: 270 The Synchronous-DRAM controller core allows any synchronous bus masters, such as most Intel microcontroller and x86 processors, to effortlessly interface to a large capacity SDRAM as though it were an SRAM. The core supports PC100 timing specific...   Category :: System controller Development status :: Alpha   system11   Updated on: 07-Apr-2008   VLM: 149 68HC11 compatible microprocessor core with monitor program, UART, and Compact Flash Interface. Does not include 68HC11 peripherals.   Category :: Microprocessor Language :: VHDL Development status :: Alpha   T8000 CPU   Updated on: 03-Jan-2006   VLM: 197 Configurable CPU that supports Z8000 (Z8001/Z8002) instruction sets.   Category :: Microprocessor Language :: Verilog Phaze :: Specification done Development status :: Alpha   TotalCPU   Updated on: 16-Jun-2007   VLM: 209 This is RISC core with 12-bit instruction width and with variable data width from 12 up to 64 bits   Category :: Microprocessor Language :: Verilog Phaze :: Design done Development status :: Alpha   Zet - The x86 (IA-32) open implementation   Updated on: 06-Oct-2008   VLM: 1560 This project implements a version of the common Intel IA-32 instruction set into a commercial FPGA.   Category :: Microprocessor Language :: Verilog License :: GPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Alpha