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Phaze :: FPGA proven We use a few icons to help identify projects: Indicates new project, that has been added in the last 30 days. Indicates project that is ready to use Indicates a WISHBONE Compliant Core VLM = Visits Last Month (how many people accessed project) 10_100_1000 Mbps tri-mode ethernet MAC   Updated on: 18-Aug-2008   VLM: 1552 10_100_1000 Mbps tri-mode ethernet MAC implements a MAC controller conforming to IEEE 802.3 specification. It is designed using less than 2000 LCs/LEs to implement full function. It will use inferred PADs to reduce technology dependancies. The wh...   Category :: Communication controller Language :: Verilog License :: LGPL Phaze :: Design done Phaze :: FPGA proven Development status :: Production/Stable   128/192 AES   Updated on: 19-Sep-2005   VLM: 425 A 128 bits and a 192 bits key length AES coprocessor focusing on very low area applications. The 128 bit implementation takes about 500 cycles to encrypt/decrypt a block. The 192 bit implementation takes about 280 cycles to encrypt/decrypt a b...   Category :: Crypto core Language :: Other Language :: Verilog Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   3DES (Triple DES) / DES (VHDL)   Updated on: 01-Dec-2006   VLM: 260 A VHDL implementation of Triple-DES (pipelined) and DES cryptographic algorithms, as recommended by NIST.   Category :: Crypto core Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable   68hc05   Updated on: 13-May-2007   VLM: 162 Rebuild of Motorola 68HC05 microcontroller only from a datasheet   Category :: Microprocessor Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable   68hc08   Updated on: 07-May-2007   VLM: 236 Rebuild of Motorola 68HC08 microcontroller only from datasheet   Category :: Microprocessor Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable   8051 Slave to Wishbone Master Interface   Updated on: 25-Jul-2008   VLM: 185 Interface an 8051-compatible microcontroller controller to the Wishbone bus.   Category :: Other Language :: Verilog Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   ACEX 1K50 board   Updated on: 11-Sep-2004   VLM: 194 A prototyping board with ACEX 1K50, 128 KB SRAM, 512 KB Flash, serial driver and wtachdog.   Category :: Prototype board License :: GPL Phaze :: FPGA proven Development status :: Mature Development status :: Production/Stable   aeMB   Updated on: 30-Jul-2008   VLM: 490 A clean room implementation of an EDK3.2 binary compatible Microblaze processor core. It is FPGA proven and has been extensively simulated using Icarus Verilog 0.8.5 and GPLCVER 2.11a to confirm performance. Simulation code is compiled using GCC ...   Category :: Microprocessor Language :: Verilog License :: LGPL Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Beta Development status :: Production/Stable   AHB to Wishbone Bridge   Updated on: 07-Sep-2007   VLM: 323 Converts AHB protocol to Wishbone protocol for interfacing two SoC's (AHB Master and Wishbone Slave).   Category :: SoC Language :: Verilog Phaze :: Design done Phaze :: FPGA proven Phaze :: Specification done Standard :: Wishbone compliant core Development status :: Mature   An Alternative Oscilloscope   Updated on: 29-Oct-2005   VLM: 350 AlternaScope provides a cheap alternative to those pricey oscilloscopes on the market. Using a VGA display and a simple mouse interface, a user can use this scope to look at and measure signals up to about 80Mhz. This kind of scope would be ide...   Category :: Other Language :: Verilog Phaze :: FPGA proven Development status :: Beta   baud generator   Updated on: 20-Dec-2007   VLM: 185 block to produce from a given clock frequency a baud rate clock and a x times baud rate enable pulse. Takes in a clock and an active high reset. Two outputs, both one clock wide active high. One at baud rate, one at x times baud rate. Param...   Category :: Communication controller Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   Bluespec Cryptosorter   Updated on: 01-Jul-2008   VLM: 73 This is a crypto sorter. Effectively, it decrypts a database, sorts it and re-encrypts it. A number of highly-reusable IP are present, including a parametric sort module. Project makes use of a number of other open cores and has been proven on...   Language :: Other Phaze :: FPGA proven Development status :: Beta   Bluespec H.264 Decoder   Updated on: 07-Jul-2008   VLM: 652 BSV implementation of H.264 Video decoder.   Category :: Video controller Language :: Other Phaze :: FPGA proven Development status :: Beta   ClaiRISC - runs 12bit opcode PIC family.   Updated on: 05-Aug-2008   VLM: 352 This is another RISC core which is compatible with the 12 bit opcode PIC family.   Category :: Microprocessor Language :: Verilog Phaze :: Design done Phaze :: FPGA proven Development status :: Production/Stable   Color Converter   Updated on: 26-Feb-2007   VLM: 343 Here is universal high precision color converter component based on the direct 3x3 matrix multiplication (see our mult3x3 arithmetic core) without convert-specific (such as RGB<->YCbCr) optimization. The current color transformation is defined b...   Category :: Video controller Dependencies :: Other cores Language :: VHDL License :: LGPL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   CORDIC core   Updated on: 14-Feb-2004   VLM: 979 The CORDIC (COordinate Rotation on a DIgital Computer) algorithm is an iterative algorithm to evaluate many mathematical functions, such as trigonometrically functions, hyperbolic functions and planar rotations.   Category :: Arithmetic core Language :: VHDL Phaze :: Design done Phaze :: FPGA proven Development status :: Production/Stable   cpu6502_tc   Updated on: 17-Apr-2008   VLM: 265 This is a VHDL IP core with True Cycle Timing for Rockwell's 6502 8-Bit CPU. With full functional input signals like ready, interrupt, non maskable interrupt and set overflow flag. Also available is the output signal sync which signals an op fetc...   Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: Design done Phaze :: FPGA proven Development status :: Production/Stable   Crypto-PAn   Updated on: 17-Feb-2007   VLM: 111 A hardware implementation of Prefix-Preserving IP Address Anonymization. The core makes use of a fully pipelined 128-bit AES (Rijndael) cipher engine as the underlying pseudorandom function, supports online key changes, and is capable of line rat...   Category :: Crypto core Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   Data Flow Processor   Updated on: 29-Feb-2008   VLM: 268 The data flow processor (DFP) is a flexible microprocessor written in VHDL which you can program down to the gate level to optimize your entire design. It is composed of 7 components with a specific data flow architecture. Please see http://www....   Category :: Microprocessor Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable   Diogenes: Student RISC System   Updated on: 04-Feb-2008   VLM: 200 This Project was developed within a Computer Architecture Course. It demonstrates a simple RISC architecture and features * Assembler * Simulator * Simple I/O (Leds, Buttons, UART, LCD) * VGA Controller Please note that it was developed ...   Category :: Microprocessor Language :: VHDL Phaze :: FPGA proven Development status :: Beta   Discrete Cosine Transform core   Updated on: 01-Jun-2008   VLM: 361 Parallel implementation of 2D DCT in VHDL. Currently works on 8 bit input data using 12 bit DCT coefficients. Multiplier-less design, distributed arithmetic used instead.   Category :: Arithmetic core Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable   DragonBall/68K Wishbone interface   Updated on: 14-Feb-2004   VLM: 181 WISHBONE Interface for Motorola's Dragonball and 68K microprocessors.   Category :: Other Language :: Verilog Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   Educational RISC Processor   Updated on: 25-Sep-2007   VLM: 341 8-bit RISC processor core written in Verilog HDL. It is capable of executing the Load, Move, Jump, Arithematic and Logical instructions. Core customization is quite simple and a lot more functionality can be included like interrupt etc.   Category :: Microprocessor Language :: Verilog Phaze :: FPGA proven Development status :: Production/Stable   EMPER E123MUX/DEMUX Core   Updated on: 10-Aug-2005   VLM: 81 FEATURES 1. E1 (2048 kbit/s) multiplexer/demultiplexer for ITU-T Recommendations: G.742 (8448 kbit/s E2 frame format) G.751 (34368 kbit/s E3 frame format) 2. Multiplexer/demultiplexer converts: 16 E1s to/from 1 E3 (E13 skip ...   Language :: Verilog Phaze :: FPGA proven Development status :: Beta   Ethernet Development Board   Updated on: 10-Nov-2005   VLM: 374 10/100 Ethernet development board featuring Altera Cyclone, SRAM, Configuration device, 5V IO, GPIO, I2C devices...   Category :: Prototype board Phaze :: FPGA proven Development status :: Production/Stable   FirGen/MultGen   Updated on: 28-Mar-2008   VLM: 336 VHDL core generator for FIR filters and Multiplier arrays with common input using "Nonrecursive Signed Common Subexpression Algorithm" for optimization program writen on C++ -------------------------- firgen [OPTION..] Aviable options ar...   Category :: DSP core Language :: Other Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   First File Reader FAT16   Updated on: 10-May-2004   VLM: 258 This Core reads from a Compact Flash attached to its IDE interface the first valid file saved into the root directory of a FAT16 volume. The data are offered to a Wishbone bus through a slave WB interface.   Category :: Other Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable   FPGA MMC-Card Config.   Updated on: 09-Jan-2005   VLM: 258 IP Core to configure RAM based FPGA from MMC Card.   Category :: Other Language :: Verilog Phaze :: FPGA proven Development status :: Production/Stable   FPU   Updated on: 29-Jun-2008   VLM: 1000 The floating point unit (FPU) implemented during this project, is a 32-bit processing unit, which does arithmetic operations on floating point numbers. The FPU complies fully with the IEEE 754 Standard.   Category :: Arithmetic core Category :: Coprocessor Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable   G9 Impulse: Video Game System   Updated on: 16-Dec-2005   VLM: 268 Custom built and designed video game system. Also includes SDK and 'release' title. All designs are open source and specification are free to be modified by the community. Specifications are currently for an early 16 bit system.   Category :: Other Phaze :: FPGA proven Development status :: Beta   Gamepads   Updated on: 15-Sep-2005   VLM: 239 A collection of cores that interface to various gamepads.   Category :: Communication controller Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Beta   Gator uProcessor - HC11 Compatible   Updated on: 04-Apr-2008   VLM: 154 Gator Microprocessor Overview * Motorola/Freescale 68xx Architecture * Source-code and machine-code compatible 68HC11 cpu core * Compatible with all HC11 C/C++ compilers including GNU GCC * Up to 100MHz operation in modern FPGAs * 2.5 t...   Category :: Microprocessor Language :: VHDL Phaze :: Design done Phaze :: FPGA proven Development status :: Production/Stable   Generic FIFOs   Updated on: 11-Feb-2004   VLM: 668 Generic, multiple purpose, parameterizable FIFOs. Single and Dual Clock.   Category :: Memory core Language :: Verilog Phaze :: FPGA proven Development status :: Production/Stable   H.264/AVC Baseline Decoder   Updated on: 06-May-2008   VLM: 1077 This is a full dedicated H.264/AVC baseline decoder. Currently it supports QCIF 30fps decoding at 1.5MHz. It contains several main building blocks, such as bitstream parsing, intra-prediction, inter-prediction, and deblocking filter. It was both ...   Category :: Video controller Language :: Verilog Phaze :: ASIC proven Phaze :: FPGA proven Development status :: Production/Stable   HiCoVec - a configurable SIMD CPU   Updated on: 06-Jun-2008   VLM: 211 The HiCoVec processor is based on a simple 32 bit scalar unit and connected with a vector unit for SIMD operations. The amount of data simultaneously processed in the vector unit can be configured as well as the amount of vector registers to h...   Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Beta   I2C controller core   Updated on: 09-Aug-2008   VLM: 3206 I2C is a two-wire, bidirectional serials bus that provide a simple, efficient method of data exchange between devices.   Category :: Communication controller Language :: Verilog Language :: VHDL Phaze :: ASIC proven Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   I2C master/slave Core   Updated on: 27-Jun-2008   VLM: 797 The design is capable of working as both I2C compatible master and slave.   Category :: Communication controller Language :: Verilog Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Beta Development status :: Production/Stable   I2S Interface   Updated on: 02-Feb-2008   VLM: 740 The I2S bus is an industry standard three-wire interface for streaming stereo audio between devices, typically between a cpu/dsp and a DAC/ADC. This core implements I2S transmitter and receiver.   Category :: Communication controller Language :: VHDL License :: GPL Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   I2S to Paralell ADC/DAC controller   Updated on: 20-Dec-2005   VLM: 232 This provides a bridge between a paralell device (such as a microcontroller (uC) and an I2C (!not! I2C) audio bus, generally used for ADC's and DAC's, such as in DVD & MP3 players   Category :: Communication controller Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Beta   JOP: a Java Optimized Processor   Updated on: 25-Aug-2008   VLM: 1275 JOP is the implementation of the Java Virtual Machine (JVM) as concrete machine in hardware. The design is full synthesizable and fits in low-cost FPGA devices from Altera and Xilinx.   Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   JPEG codec library based on microblaze   Updated on: 12-Mar-2008   VLM: 596 This is an open source JPEG codec, including both encoder and decoder, for embedded systems. It can be fully synthesized and implemented on FPGA. Different to a fully hardware implementation, this JPEG codec is designed based on Xilinx Microbl...   Category :: Video controller Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   JPEG Hardware Compressor   Updated on: 25-Feb-2008   VLM: 804 This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second (on XC2V1000-4 @ 40 MHz with resolution 352x288). Image resolution is...   Category :: Video controller Language :: VHDL License :: LGPL Phaze :: FPGA proven Development status :: Production/Stable   keyboardcontroller   Updated on: 06-Jul-2005   VLM: 230 A simple keyboard controller that works by scanning a matrix. It requires the inputs to be pull-up high. After scanning the matrix and detecting a keypress-release it generates the corresponding translated set2 scancode. This controller also p...   Category :: Other Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   Lightweight 8080 compatible core   Updated on: 19-Aug-2008   VLM: 325 Small, microprogrammed 8080-compatible cpu core. Emphasis on area reduction and design simplicity.   Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Alpha   LPC ROM emulator on USB dongle FPGA core set   Updated on: 21-Jul-2008   VLM: 442 This is ROM emulator/debugger hardware project in a USB dongle board format containing: Cyclone FPGA EP1C6T144C8N Serial Platform Flash Intel Strata Flash E28F128 (16MB) in 16 bit mode FTDI parallel to USB bridge FT245BM 4 segment LED displ...   Category :: Prototype board Category :: Communication controller Language :: VHDL License :: LGPL Phaze :: FPGA proven Development status :: Production/Stable   Manchester to UART converter   Updated on: 24-Nov-2004   VLM: 219 Bi-phase signal in Bosch Manchester Format send from Bosch control Keyboard Convert to UART signal.   Category :: Communication controller Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable   McAdam's RISC Computer Architecture   Updated on: 02-Feb-2007   VLM: 185 marca is a simple 16-bit microprocessor, implementing a load/store instruction set architecture and featuring a 4-stage pipeline.   Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   MCPU - A minimal CPU for a CPLD   Updated on: 29-Jul-2008   VLM: 808 mcpu is a minimal cpu designed to fit into a 32 macrocell CPLD. 4 Instructions and access to 64 bytes of memory are supported. Sourcecode is provided in VHDL and Verilog and occupies only a single printed page.   Category :: Microprocessor Language :: Verilog Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Mature Development status :: Production/Stable