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Language :: Other We use a few icons to help identify projects: Indicates new project, that has been added in the last 30 days. Indicates project that is ready to use Indicates a WISHBONE Compliant Core VLM = Visits Last Month (how many people accessed project) 128/192 AES   Updated on: 19-Sep-2005   VLM: 419 A 128 bits and a 192 bits key length AES coprocessor focusing on very low area applications. The 128 bit implementation takes about 500 cycles to encrypt/decrypt a block. The 192 bit implementation takes about 280 cycles to encrypt/decrypt a b...   Category :: Crypto core Language :: Other Language :: Verilog Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   Bluespec 802.11a Transmitter   Updated on: 02-Jul-2008   VLM: 227 This Project is the implementation of a 80.211a Transmitter baseband block in BSV (Bluespec SystemVerilog).   Category :: Communication controller Language :: Other Development status :: Production/Stable   Bluespec Board Support Packages   Updated on: 27-Jun-2008   VLM: 94 Common components needed to instantiate Bluespec designs on common FPGA, ASIC, and simulation platforms. For example, wrappers for different memories, memory controllers, and peripherals.   Category :: Library Language :: Other   Bluespec Cryptosorter   Updated on: 01-Jul-2008   VLM: 74 This is a crypto sorter. Effectively, it decrypts a database, sorts it and re-encrypts it. A number of highly-reusable IP are present, including a parametric sort module. Project makes use of a number of other open cores and has been proven on...   Language :: Other Phaze :: FPGA proven Development status :: Beta   Bluespec H.264 Decoder   Updated on: 07-Jul-2008   VLM: 622 BSV implementation of H.264 Video decoder.   Category :: Video controller Language :: Other Phaze :: FPGA proven Development status :: Beta   Confluence OpenRisc 1000   Updated on: 17-Jun-2004   VLM: 128 This is a Confluence implementation of the OpenRisc 1000 architecture.   Category :: Microprocessor Language :: Other Development status :: Alpha   FirGen/MultGen   Updated on: 28-Mar-2008   VLM: 366 VHDL core generator for FIR filters and Multiplier arrays with common input using "Nonrecursive Signed Common Subexpression Algorithm" for optimization program writen on C++ -------------------------- firgen [OPTION..] Aviable options ar...   Category :: DSP core Language :: Other Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   High Speed SDRAM Controller With Adaptive Bank Management and Command Pipeline   Updated on: 23-Aug-2008   VLM: 670 HSSDRC is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. The main features of HSSDRC IP core are: 1. Adaptive SDRAM bank control : command sequence is depending upon previous accesses to...   Category :: Memory core Language :: Other Phaze :: Design done Development status :: Alpha Development status :: Production/Stable   HyperTransport Tunnel   Updated on: 23-May-2006   VLM: 167 A HyperTransport Tunnel controller written in SystemC. HyperTransport (HT) is a high-performance chip-to-chip interconnect architecture. A tunnel has two HT ports to allow it to be used inside a chain of components.   Category :: Communication controller Language :: Other Phaze :: Design done Development status :: Beta   IIE-PCI Board   Updated on: 06-Jul-2005   VLM: 280 The IIE-PCI Development Platform board is a low cost PCI device card with a programmable logic chip (Altera ACEX), dynamic ram, and expansion capabilities. The main purpose of the IIE-PCI board is to test PCI designs in a educational environme...   Category :: Prototype board Language :: Other License :: GPL Development status :: Production/Stable   OpenRisc 1200 Graphic Configuration Tool   Updated on: 16-Sep-2005   VLM: 139 A Tcl/TK script to graphically configure OpenRisc 1200 microprocessor. Similar to LEON one.   Category :: Other Language :: Other License :: GPL Phaze :: Design done Development status :: Production/Stable   PCI Express x1 16bit VERA testbench   Updated on: 15-Jan-2008   VLM: 349 This is a great starter testbench for PCI Express. It performs link management; Initial Flow control; tlp packet generation. It includes lcrc generation; scrambling/descrambling and   Category :: System controller Language :: Other Phaze :: Design done   ROSETTA Configurable Dot Matrix Display Controller   Updated on: 12-Jun-2006   VLM: 226 The ROSETTA Configurable Dot Matrix Display Controller core provides a modular expandable interface for any dimension displays build from LEDs dot matrix structures. This core can be configured for synthesis and P&R with any number of DM LEDs s...   Category :: Video controller Language :: Other Language :: Verilog Language :: VHDL License :: GPL Phaze :: Specification done Standard :: Wishbone compliant core Development status :: Planning   SardMIPS   Updated on: 09-Feb-2006   VLM: 187 It's a synthesizable parametric IP core of 32 bit RISC processor supporting full MIPS R2000 ISA, by using SystemC HDL. An optional CP0 coprocessor implementing full exception handling was also modelled. Also 64 bit pipeline multiplier supporting ...   Category :: Microprocessor Category :: SoC Language :: Other License :: GPL Development status :: Alpha   SD/MMC/SPIflash FPGA Config   Updated on: 13-Apr-2008   VLM: 468 Store FPGA configuration files in SD/MMC cards, or SPI flash, and load into FPGA using cheap microprocessor. Very low component count, configures FPGA at 2Mbps, download files from PC to flash at 400Kbps.   Category :: Other Language :: Other Development status :: Production/Stable   SystemC USB1.1 IP Core   Updated on: 09-Jul-2004   VLM: 206 The USB1.1 Function IP Core and dependencies, maintained by Rudolf Usselmann, translated into SystemC. The SystemC...   Category :: Communication controller Language :: Other Phaze :: Design done Development status :: Production/Stable   SystemC/Verilog DES   Updated on: 19-Sep-2005   VLM: 182 An area improved DES coprocessor and his equivalent Verilog description.   Category :: Crypto core Language :: Other Language :: Verilog Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   SystemC/Verilog MD5   Updated on: 15-Sep-2005   VLM: 185 A MD5 hash algorithm implementation in SystemC, including the equivalent synthesizable Verilog translation   Category :: Crypto core Language :: Other Language :: Verilog License :: LGPL Phaze :: FPGA proven Development status :: Production/Stable   SystemC/Verilog Random Number Generator   Updated on: 20-Mar-2008   VLM: 304 A 32 bits random number generator based on the combination of a LFSR and a CASR, that gives very good statisticall properties   Category :: Other Language :: Other Language :: Verilog License :: LGPL Phaze :: FPGA proven Development status :: Production/Stable   TI DSP and Xilinx FPGA Dev Board   Updated on: 13-Dec-2005   VLM: 585 An FPGA and DSP development board with cPCI interface. Project aims to provide a low cost development platform for DSP and FPGA algorithms implementation. The dev board provides several means for interfacing user-developed hardware. This project ...   Category :: Prototype board Category :: System controller Language :: Other Language :: Verilog Phaze :: Design done Development status :: Production/Stable   Video Starter Kit   Updated on: 27-Nov-2006   VLM: 915 This Video Starter kit is meant for people who want to start with FPGA design. The kit can be used with free tooling only. There is no need for an extra JTAG device or so. (only needed for on-chip debugging) Within the project there will be ...   Category :: Prototype board Category :: Video controller Language :: Other Language :: VHDL Development status :: Beta   Viterbi HDL Code Generator   Updated on: 10-May-2006   VLM: 366 This is one HDL code generator of some kinds of Viterbi decoders. Now it can only generate Verilog HDL code. I hope somebody will improve this generator for the special applications. It would be licensed under GPL, I think. But the HDL code will ...   Category :: Arithmetic core Language :: Other License :: GPL Phaze :: Design done Development status :: Beta   WB/OPB & OPB/WB Interface Wrapper   Updated on: 12-Sep-2004   VLM: 138 Interface wrappers between OPB and WISHBONE buses   Category :: SoC Language :: Other Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable