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Category :: Other We use a few icons to help identify projects: Indicates new project, that has been added in the last 30 days. Indicates project that is ready to use Indicates a WISHBONE Compliant Core VLM = Visits Last Month (how many people accessed project) 8051 Slave to Wishbone Master Interface   Updated on: 25-Jul-2008   VLM: 181 Interface an 8051-compatible microcontroller controller to the Wishbone bus.   Category :: Other Language :: Verilog Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   a VHDL 8254 Timer   Updated on: 24-Aug-2008   VLM: 739 a VHDL timer, based upon the Intel 8254   Category :: Other Dependencies :: Other cores Language :: VHDL Phaze :: Design done Development status :: Production/Stable   An Alternative Oscilloscope   Updated on: 29-Oct-2005   VLM: 358 AlternaScope provides a cheap alternative to those pricey oscilloscopes on the market. Using a VGA display and a simple mouse interface, a user can use this scope to look at and measure signals up to about 80Mhz. This kind of scope would be ide...   Category :: Other Language :: Verilog Phaze :: FPGA proven Development status :: Beta   BigCounter   Updated on: 02-Jan-2008   VLM: 142 Uses the shift register technology to create a big counter, that gives out a pulse at the period specified as a generic.   Category :: Other Language :: VHDL License :: GPL Development status :: Beta   boundaries   Updated on: 07-Jul-2004   VLM: 139 A collection of useful multi-clock and clock-boundary designs.   Category :: Other Language :: Verilog Phaze :: Design done Development status :: Production/Stable   DragonBall/68K Wishbone interface   Updated on: 14-Feb-2004   VLM: 184 WISHBONE Interface for Motorola's Dragonball and 68K microprocessors.   Category :: Other Language :: Verilog Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   DWT coprocessor on still image   Updated on: 24-Jan-2005   VLM: 127 This core implements Forward and Inverse Discrete Wavelet Transform (FDWT and IDWT) on still image. Wavelet LeGall 5/3 is selected in design. The project is simulated on ModelSim 5.7g and going to implement on Spartan-3 Starter Kit.   Category :: Other Language :: VHDL Development status :: Beta   First File Reader FAT16   Updated on: 10-May-2004   VLM: 253 This Core reads from a Compact Flash attached to its IDE interface the first valid file saved into the root directory of a FAT16 volume. The data are offered to a Wishbone bus through a slave WB interface.   Category :: Other Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable   FPGA MMC-Card Config.   Updated on: 09-Jan-2005   VLM: 263 IP Core to configure RAM based FPGA from MMC Card.   Category :: Other Language :: Verilog Phaze :: FPGA proven Development status :: Production/Stable   Fuzzy Logic Hardware Accelerator   Updated on: 07-Apr-2004   VLM: 152 This project is to design a Fuzzy Logic Hardware Accelerator (FLHA) that is WishBone compatible. FLHA is capable of generating fuzzy rule matrix and inference for it. The input and output data will be 64-bit. Each input and output data will have ...   Category :: Other Language :: VHDL License :: GPL Development status :: Beta   G9 Impulse: Video Game System   Updated on: 16-Dec-2005   VLM: 271 Custom built and designed video game system. Also includes SDK and 'release' title. All designs are open source and specification are free to be modified by the community. Specifications are currently for an early 16 bit system.   Category :: Other Phaze :: FPGA proven Development status :: Beta   gsc   Updated on: 28-Aug-2007   VLM: 200 gnu systemc compiler - a systemc collection of tools, including a systemc to verilog translator.   Category :: Other Language :: SystemC Language :: Verilog License :: GPL Development status :: Beta Development status :: Production/Stable   Hardware looping unit   Updated on: 19-Oct-2006   VLM: 137 Tha main purpose of the hardware looping unit (HWLU) is to enhance program control units found in modern microprocessors, by efficiently handling loop increments and branches in nested loop structures. It is based on recently published work (deta...   Category :: Other Language :: VHDL License :: GPL Phaze :: Design done Development status :: Production/Stable   In System Programming via JTAG port   Updated on: 19-Jul-2008   VLM: 193 With a PC program, a JTAG cable, and a JTAG ciruit (realized in a cpld), you can program a memory chip, such as Flash or EEprom.   Category :: Other Language :: Verilog Development status :: Planning   JTAG Test Access Port (TAP)   Updated on: 28-Jan-2004   VLM: 550 This implementation of the Test Access Port (TAP) is fully IEEE 1149.1 compliant.   Category :: Other Development status :: Production/Stable   keyboardcontroller   Updated on: 06-Jul-2005   VLM: 232 A simple keyboard controller that works by scanning a matrix. It requires the inputs to be pull-up high. After scanning the matrix and detecting a keypress-release it generates the corresponding translated set2 scancode. This controller also p...   Category :: Other Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   Keypad Scanner   Updated on: 16-Jun-2003   VLM: 201 Parameterized module that scans an (X,Y) keypad matrix and reports which key is pressed. Variable scan rate, provides registered outputs.   Category :: Other Standard :: Wishbone compliant core Development status :: Production/Stable   Ogg Vorbis Encoder/Decoder for Virtex-II Pro   Updated on: 31-Mar-2004   VLM: 156 I am starting a project to implement an Ogg Vorbis Encoder or Decoder for the Xilinx Virtex-II Pro platform. I hope to take advantage of architecture specific items like block rams and multipliers. I'd like to target the XC2VP7 parts and progra...   Category :: Other Development status :: Planning   OpenRisc 1200 Graphic Configuration Tool   Updated on: 16-Sep-2005   VLM: 140 A Tcl/TK script to graphically configure OpenRisc 1200 microprocessor. Similar to LEON one.   Category :: Other Language :: Other License :: GPL Phaze :: Design done Development status :: Production/Stable   Perlilog   Updated on: 06-Mar-2004   VLM: 795 Perlilog is a design tool, whose main target is easy integration of Verilog IP cores for System-on-Chip (SoC) designs. It's also a good starting point for writing scripts which handle Verilog code in general   Category :: Other Development status :: Beta   Picoblaze's Interrupt Controller   Updated on: 22-Dec-2006   VLM: 168 Picoblaze's interrupt controller expands picoblaze's interrupt into n-interrupt sources (up to 8-interrupts are supported). The controller is put as input port. If interrupt occurs, the firmware will need to read this port, do some interrupt ...   Category :: Other Language :: VHDL Phaze :: Design done Development status :: Beta   PS2 interface   Updated on: 03-Jul-2005   VLM: 321 The PS/2 interface project (ps2_interface) is interface hardware to allow using a ps2 mouse or keyboard in your project. The code is written in Verilog, and was sythesized into a Xilinx SpartanII XC2S200 chip. Debugging was done with an HP16500 s...   Category :: Other Development status :: Production/Stable   PWM/Timer/Counter (PTC) Core   Updated on: 17-Nov-2006   VLM: 366 PWM/Timer/Counter (PTC) IP core is a user-programmable PWM, Timer and Counter controller. Its use is to implement functions like Pulse Width Modulation (PWM), timer and counter facilities.   Category :: Other Standard :: Wishbone compliant core Development status :: Production/Stable   Scalable Arbiter   Updated on: 08-Aug-2008   VLM: 426 A scalable synchronous round-robin arbiter. The arbiter is designed to run at reasonable clock speeds with up to hundreds of request lines, and it grants in just a few clock cycles. The arbiter's interface has individual request and grant lines f...   Category :: Other Language :: Verilog Development status :: Beta   SD/MMC/SPIflash FPGA Config   Updated on: 13-Apr-2008   VLM: 469 Store FPGA configuration files in SD/MMC cards, or SPI flash, and load into FPGA using cheap microprocessor. Very low component count, configures FPGA at 2Mbps, download files from PC to flash at 400Kbps.   Category :: Other Language :: Other Development status :: Production/Stable   Simple All Digital FM Receiver   Updated on: 26-Oct-2006   VLM: 406 The design of the All Digital FM Receiver circuit in this project uses Phase Locked Loop (PLL) as the main core. The task of the PLL is to maintain coherence between the input (modulated) signal frequency, and the respective output frequency, via...   Category :: Other Language :: VHDL License :: GPL Phaze :: Design done Phaze :: FPGA proven Development status :: Alpha   Simple FM Receiver   Updated on: 10-Aug-2008   VLM: 824 Simple FM Receiver to demodulate signal FM (square wave signal modulated in FM)   Category :: Other Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable   Simple General Purpose IO   Updated on: 14-Feb-2004   VLM: 249 Simple General Purpose IO core.   Category :: Other Language :: Verilog Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   Simple Programmable Interrupt Controller   Updated on: 04-Mar-2008   VLM: 253 Simple programmable Interrupt Controller. Supports 8 interrupt sources. Programmable Level/Edge sensitivity and Polarity per interrupt source.   Category :: Other Language :: Verilog Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   Simple Traffic Light Controller for modelmaking purposes   Updated on: 18-Jun-2008   VLM: 141 The goal of this project is to provide a simple traffic light controller for different transport modeling purposes like model railways.   Category :: Other Language :: VHDL License :: LGPL Phaze :: FPGA proven Development status :: Production/Stable   SoC Debug Interface   Updated on: 24-May-2007   VLM: 316 Development Interface is used for development purposes (Boundary Scan testing and debugging).   Category :: Other Standard :: Wishbone compliant core Development status :: Production/Stable   SONET/SDHframer   Updated on: 04-Mar-2003   VLM: 116 Want to work on creating IP for SONET/SDH framer/add-drop mux/mapper. Looking for a team who wants to start such a project.   Category :: Other Development status :: Planning   SystemC to Verilog Synthesizable Subset Translator   Updated on: 19-Mar-2007   VLM: 227 Translates a SystemC RT description to a Verilog equivalent one   Category :: Other Phaze :: Design done Development status :: Production/Stable   SystemC/Verilog Random Number Generator   Updated on: 20-Mar-2008   VLM: 301 A 32 bits random number generator based on the combination of a LFSR and a CASR, that gives very good statisticall properties   Category :: Other Language :: Other Language :: Verilog License :: LGPL Phaze :: FPGA proven Development status :: Production/Stable   The VHDL Test Bench   Updated on: 24-Feb-2008   VLM: 277 The VHDL test bench is a collection of VHDL procedures and functions which allow the user to create their own scripting instructions for test stimulus. The stimulus script or test case contains the instructions in a regular ASCII text file. The ...   Category :: Other Language :: VHDL License :: GPL Development status :: Production/Stable   Universal Programming Cable   Updated on: 03-Dec-2004   VLM: 426 Universal Programming Cable, based on PLD technology can be used to emulate other simple LPT based programming cables. The benefit is that you only need one Cable and can use it Xilinx Cable III or Byteblaster II, or Altera ISP cable or some othe...   Category :: Prototype board Category :: Other Language :: Verilog Language :: VHDL Phaze :: FPGA proven   VHDL File-based CPU Emulator   Updated on: 01-Jun-2006   VLM: 160 This project emulates a CPU for an FPGA under simulation with the use of text files. It can be used to test an FPGA - CPU interface using realistic real-world stimuli. One main text file per CPU emulation instance is used for global CPU commands,...   Category :: Other Language :: VHDL License :: GPL Development status :: Beta   WB Interface for TI 5x DSP (WB2HPI)   Updated on: 20-Feb-2004   VLM: 174 Wishbone Interface for TI 5x DSP   Category :: Other Standard :: Wishbone compliant core Development status :: Production/Stable   wb_rtc   Updated on: 20-Sep-2003   VLM: 113 a real time clock IP core with wishbone bus compatible.   Category :: Other Development status :: Planning   xmatchpro lossless data compressor   Updated on: 14-Jun-2007   VLM: 154 high-throughput parallel lossless data compressor/decompressor core   Category :: Other Language :: VHDL License :: LGPL Phaze :: FPGA proven Development status :: Production/Stable