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Category :: Microprocessor We use a few icons to help identify projects: Indicates new project, that has been added in the last 30 days. Indicates project that is ready to use Indicates a WISHBONE Compliant Core VLM = Visits Last Month (how many people accessed project) 1-bit Microprocessor   Updated on: 17-Oct-2006   VLM: 482 This project, in VHDL, implements a single-bit microprocessor based on the now obsolete Motorola MC14500B Industrial Control Unit. The ICU is basically a logic sequencer with a 4-bit instruction unit (16-instructions). In addition to the ICU, t...   Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: Design done Development status :: Alpha   16 Bit Microcontroller   Updated on: 16-Apr-2006   VLM: 555 This is A 16 bit CPU, optimized for the execution of C programs. The CPU requires about 800 Xilinx slices, or about 1000 slices for a complete system on a chip with serial I/O and a few other I/O interfaces. The CPU comes with an assembler,...   Category :: Microprocessor Standard :: Wishbone compliant core Development status :: Production/Stable   6502VHDL   Updated on: 22-Dec-2003   VLM: 239 the goal of the project is to create a synthesizable core for the 6502 microprocessor. The initial target will be XILINX fpga devices. A prototype version will be running on the Digilent (digilentinc.com) spartan2E board.   Category :: Microprocessor Development status :: Planning   68hc05   Updated on: 13-May-2007   VLM: 165 Rebuild of Motorola 68HC05 microcontroller only from a datasheet   Category :: Microprocessor Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable   68hc08   Updated on: 07-May-2007   VLM: 232 Rebuild of Motorola 68HC08 microcontroller only from datasheet   Category :: Microprocessor Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable   8-bit microcontroller with extended peripheral set   Updated on: 10-Aug-2008   VLM: 515 The goal of this project is to create a very well documented, fully synthesizable VHDL model of an 8-bit microcontroller with extended peripheral set. The model should be highly configurable, making it possible to exclude unused peripheral units....   Category :: Microprocessor Language :: VHDL License :: LGPL Development status :: Alpha   8051 core   Updated on: 29-Jul-2008   VLM: 1384 The basic form of 8051 core includes several on-chip peripherals, like timers and counters, additionally there are 128 bytes of on-chip data memory and up to 64K bytes of on-chip program memory.   Category :: Microprocessor Standard :: Wishbone compliant core Development status :: Alpha   8080 Compatible CPU   Updated on: 21-Nov-2006   VLM: 505 CPU8080 is a basic 8080 emulation in Verilog. It was completed as a project to learn Verilog, but it can be useful as a very small onchip controller CPU with very modest silicon area requirements. In addition, the 8080 has a long list of softw...   Category :: Microprocessor Language :: Verilog Phaze :: Design done Development status :: Production/Stable   ae18   Updated on: 11-Oct-2007   VLM: 241 A synthesizable core of the PIC18 cpu. It is capable of executing all PIC18 codes. It has been extensively simulated using Icarus Verilog 0.8.2 and GPLCVER 2.11a to confirm performance. The code is compiled using SDCC 2.5 and GPASM 0.13.4. Synthe...   Category :: Microprocessor Language :: Verilog License :: LGPL Phaze :: Design done Standard :: Wishbone compliant core Development status :: Beta Development status :: Production/Stable   aeMB   Updated on: 30-Jul-2008   VLM: 459 A clean room implementation of an EDK3.2 binary compatible Microblaze processor core. It is FPGA proven and has been extensively simulated using Icarus Verilog 0.8.5 and GPLCVER 2.11a to confirm performance. Simulation code is compiled using GCC ...   Category :: Microprocessor Language :: Verilog License :: LGPL Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Beta Development status :: Production/Stable   Aquarius   Updated on: 04-Jul-2004   VLM: 277 Aquarius is an IP core of pipelined RISC CPU, which is compatible with instruction set of SuperH-2.   Category :: Microprocessor Standard :: Wishbone compliant core Development status :: Production/Stable   Arm core   Updated on: 26-Apr-2004   VLM: 1030 A free synthesizable arm v4 vhdl model. The framework is made to be extendable for other architectures in the future.   Category :: Microprocessor Category :: SoC Language :: VHDL Development status :: Beta   ASPIDA sync/async DLX Core   Updated on: 23-Sep-2005   VLM: 212 The ASPIDA (ASynchronous Processor Ip of the Dlx Architecture) project aims to demonstrate the industrial viability and IP Reuse potential of asynchronous parts by delivering a free, open-source, industrial-quality, asynchronous IP Processor Core...   Category :: Microprocessor Standard :: Wishbone compliant core Development status :: Production/Stable   AVR Core   Updated on: 30-Aug-2008   VLM: 1375 AVR core, UART, Timer/Counter and parallel ports   Category :: Microprocessor Development status :: Production/Stable   AX8 mcu   Updated on: 06-Mar-2007   VLM: 278 90S1200/2313 microcontroller core   Category :: Microprocessor Development status :: Production/Stable   CF State Space Processor   Updated on: 08-May-2008   VLM: 176 Confluence generated state space processor for multivariable linear systems.   Category :: Microprocessor Development status :: Production/Stable   ClaiRISC - runs 12bit opcode PIC family.   Updated on: 05-Aug-2008   VLM: 245 This is another RISC core which is compatible with the 12 bit opcode PIC family.   Category :: Microprocessor Language :: Verilog Phaze :: Design done Phaze :: FPGA proven Development status :: Production/Stable   Confluence OpenRisc 1000   Updated on: 17-Jun-2004   VLM: 128 This is a Confluence implementation of the OpenRisc 1000 architecture.   Category :: Microprocessor Language :: Other Development status :: Alpha   Cowgirl   Updated on: 31-May-2007   VLM: 312 This is a processor core based on an instruction set I came up with. It's mostly a copy of a MIPS-type RISC architecture. Right now it's in the fairly early stages, but it is working for ~80% of the instructions.   Category :: Microprocessor Language :: VHDL Phaze :: Design done Development status :: Beta   Cpu Generator   Updated on: 03-Mar-2004   VLM: 460 CpuGen (TM) generates customizable RISC cpu cores. It allows direct customization of address/data/instruction bus size, interrupt handling, indirect addressing, data/instruction latency timings and custom instructions definition. It is targeted...   Category :: Microprocessor Language :: VHDL Development status :: Production/Stable   cpu6502_tc   Updated on: 17-Apr-2008   VLM: 280 This is a VHDL IP core with True Cycle Timing for Rockwell's 6502 8-Bit CPU. With full functional input signals like ready, interrupt, non maskable interrupt and set overflow flag. Also available is the output signal sync which signals an op fetc...   Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: Design done Phaze :: FPGA proven Development status :: Production/Stable   cpu65c02_tc - 65C02 Processor Soft Core with accurate timing   Updated on: 13-Aug-2008   VLM: 297 The 65C02 is the upgraded version of the legendary R6502. cpu65c02_tc offers you an accurate timing for all new and upgraded op codes of the 65C02. This soft core was generated in VHDL and designed with Mentor's HDL Designer. It comes also with ...   Category :: Microprocessor Language :: VHDL License :: GPL Development status :: Beta   Data Flow Processor   Updated on: 29-Feb-2008   VLM: 258 The data flow processor (DFP) is a flexible microprocessor written in VHDL which you can program down to the gate level to optimize your entire design. It is composed of 7 components with a specific data flow architecture. Please see http://www....   Category :: Microprocessor Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable   Diogenes: Student RISC System   Updated on: 04-Feb-2008   VLM: 178 This Project was developed within a Computer Architecture Course. It demonstrates a simple RISC architecture and features * Assembler * Simulator * Simple I/O (Leds, Buttons, UART, LCD) * VGA Controller Please note that it was developed ...   Category :: Microprocessor Language :: VHDL Phaze :: FPGA proven Development status :: Beta   Educational RISC Processor   Updated on: 25-Sep-2007   VLM: 335 8-bit RISC processor core written in Verilog HDL. It is capable of executing the Load, Move, Jump, Arithematic and Logical instructions. Core customization is quite simple and a lot more functionality can be included like interrupt etc.   Category :: Microprocessor Language :: Verilog Phaze :: FPGA proven Development status :: Production/Stable   embedded z8 µController core   Updated on: 15-Mar-2007   VLM: 164 The Z8 family from Zilog represents a flexible 8 bit microcontroller architecture, which are suitable for embedded applications.   Category :: Microprocessor Development status :: Alpha   Free-Standing O-O Processor   Updated on: 20-Mar-2007   VLM: 214 To design a free-standing, reentrant, parallelizable object-oriented processor.   Category :: Microprocessor Development status :: Planning   Gator uProcessor - HC11 Compatible   Updated on: 04-Apr-2008   VLM: 171 Gator Microprocessor Overview * Motorola/Freescale 68xx Architecture * Source-code and machine-code compatible 68HC11 cpu core * Compatible with all HC11 C/C++ compilers including GNU GCC * Up to 100MHz operation in modern FPGAs * 2.5 t...   Category :: Microprocessor Language :: VHDL Phaze :: Design done Phaze :: FPGA proven Development status :: Production/Stable   HiCoVec - a configurable SIMD CPU   Updated on: 06-Jun-2008   VLM: 207 The HiCoVec processor is based on a simple 32 bit scalar unit and connected with a vector unit for SIMD operations. The amount of data simultaneously processed in the vector unit can be configured as well as the amount of vector registers to h...   Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Beta   HPC-16   Updated on: 08-Nov-2006   VLM: 159 Simple 16-bit microprocessor, 15-general purpose registers. custom instruction set, load-store RISC but current implementation non piplined, control unit hardwired, 64K address space, total 16-interrupts (10 maskable), memory mapped i/o. design w...   Category :: Microprocessor Language :: VHDL License :: LGPL Phaze :: Design done Development status :: Beta   HyperMTA   Updated on: 27-Apr-2002   VLM: 161 Super multithreaded architecture. VLIW Based core with many threads customizable to perform between 32 and 256 threads(estimated).   Category :: Microprocessor Development status :: Planning   JOP: a Java Optimized Processor   Updated on: 07-Sep-2008   VLM: 1266 JOP is the implementation of the Java Virtual Machine (JVM) as concrete machine in hardware. The design is full synthesizable and fits in low-cost FPGA devices from Altera and Xilinx.   Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   Lightweight 8080 compatible core   Updated on: 19-Aug-2008   VLM: 339 Small, microprogrammed 8080-compatible cpu core. Emphasis on area reduction and design simplicity.   Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Alpha   LocationPU   Updated on: 06-Feb-2002   VLM: 129 This processor performs operations according to the memory positons the data is in. It has a smaller processor which runs threads. Threads only perform actions on pointers. These pointers move data from one position to another position to have...   Category :: Microprocessor Development status :: Planning   M1 Core   Updated on: 22-Aug-2008   VLM: 444 The M1 Core is a 32-bit RISC CPU compatible with GCC. It is so simple that it can be used for didactical purposes.   Category :: Microprocessor Language :: Verilog License :: GPL Phaze :: Specification done Development status :: Beta   McAdam's RISC Computer Architecture   Updated on: 02-Feb-2007   VLM: 184 marca is a simple 16-bit microprocessor, implementing a load/store instruction set architecture and featuring a 4-stage pipeline.   Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   MCPU - A minimal CPU for a CPLD   Updated on: 29-Jul-2008   VLM: 673 mcpu is a minimal cpu designed to fit into a 32 macrocell CPLD. 4 Instructions and access to 64 bytes of memory are supported. Sourcecode is provided in VHDL and Verilog and occupies only a single printed page.   Category :: Microprocessor Language :: Verilog Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Mature Development status :: Production/Stable   MicroRISC II   Updated on: 01-Apr-2002   VLM: 208 5 Stage Pipeline RISC Core for embedded control of devices. Optimized for the SpartanII and Virtex line of FPGA's.   Category :: Microprocessor Development status :: Alpha   Mini-Risc core   Updated on: 22-May-2007   VLM: 882 This is a Mini-RISC CPU/Microcontroller that is compatible with the PIC 16C57 from Microchip. Additional information about the instruction set and capabilities can be found at: www.microchip.com   Category :: Microprocessor Language :: Verilog Development status :: Production/Stable   miniMIPS   Updated on: 24-Mar-2006   VLM: 486 The miniMIPS is a 5 stage pipeline based on the MIPS I instruction set which is a 32 bits RISC architecture. Nearly all the instructions are supported with some custom feaures added. The core has been prototyped on an FPGA during an internship....   Category :: Microprocessor Language :: VHDL License :: LGPL Phaze :: FPGA proven Development status :: Production/Stable   mips789   Updated on: 07-Apr-2008   VLM: 311 This is a ip cpu core with five pipeline stages which supports amost MIPSI instructions.I tested is by using a lot of C program in the CYCLONE device EP1C6Q240 with 50MHZ and it worked so well .By calculation ,it's CPI is about 1.1 when run comm...   Category :: Microprocessor Language :: Verilog Phaze :: FPGA proven Development status :: Production/Stable   nCore   Updated on: 28-Oct-2007   VLM: 197 This is a little-little processor core. It has 16 instructions. It is under developement again, since the latest version is deleted... It is not yet verified, tested, etc. but it's ready to compile.   Category :: Microprocessor Language :: Verilog License :: GPL Development status :: Alpha   nnARM core   Updated on: 15-Oct-2001   VLM: 686 ARM-7 clone   Category :: Microprocessor Standard :: Wishbone compliant core Development status :: Mature   oks8   Updated on: 24-Jan-2006   VLM: 166 oks8 is intended to provide a microcontroller in Verilog that like the KS86C4204/C4208/P4208 microcontroller (Samsung Inc.).   Category :: Microprocessor Language :: Verilog License :: GPL Standard :: Wishbone compliant core Development status :: Alpha   Open8 uRISC   Updated on: 28-Nov-2007   VLM: 222 This is a "clean" reimplementation of the Vautomation uRISC/Arclite 8-bit RISC processor. It is being created from specifications and opcode maps, with a few additions. (it is a superset of the original ISA) This processor core was originally ...   Category :: Microprocessor Language :: VHDL Development status :: Production/Stable   OpenCores54x DSP   Updated on: 20-Jan-2004   VLM: 432 The OC54x DSP is a cleanroom implementation of a popular family of DSPs.   Category :: Microprocessor Standard :: Wishbone compliant core Development status :: Beta   OpenFIRE   Updated on: 16-Oct-2007   VLM: 394 The OpenFire soft processor is an open source Verilog implementation of the Xilinx MicroBlaze. Like the MicroBlaze, the OpenFire is a 32-bit RISC processor based on the DLX architecture by Hennessy and Patterson. The OpenFire was developed by S...   Category :: Microprocessor Category :: SoC Language :: Verilog Phaze :: FPGA proven Development status :: Beta   OpenFire Processor Core   Updated on: 13-Dec-2007   VLM: 232 The OpenFire soft processor is an open source Verilog implementation of the Xilinx MicroBlaze processor. Like the MicroBlaze, the OpenFire is a 32-bit RISC processor based on the DLX architecture by Hennessy and Patterson. The OpenFire processor...   Category :: Microprocessor Language :: Verilog Phaze :: FPGA proven Development status :: Alpha   OpenRISC 1000   Updated on: 06-Sep-2008   VLM: 12146 OpenRISC 1000 is an architecture of a family of open source, synthesizable RISC microprocessor cores. It is a 32-bit load and store RISC architecture designed with emphasis on speed, compact instruction set and scalability. OpenRISC 1000 targets ...   Category :: Microprocessor Language :: Verilog License :: LGPL Phaze :: ASIC proven Standard :: Wishbone compliant core Development status :: Production/Stable   OpenRISC 2000   Updated on: 20-Jan-2004   VLM: 560 A novel processor architecture based on dataflow architecture techniques and with support for SMT is proposed. Analysis indicates that instructions are normally not dependent on all registers in register file. Since there are many hazards due to ...   Category :: Microprocessor Development status :: Beta   pAVR   Updated on: 22-Aug-2006   VLM: 371 pAVR (pipelined AVR) is an 8 bit RISC controller, compatible with Atmel's AVR core, but about 3x faster in terms of both clock frequency and MIPS. It achieves this performance by using a deep pipeline (with 6 stages).   Category :: Microprocessor Development status :: Alpha   Plasma - most MIPS I(TM) opcodes