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Category :: Library We use a few icons to help identify projects: Indicates new project, that has been added in the last 30 days. Indicates project that is ready to use Indicates a WISHBONE Compliant Core VLM = Visits Last Month (how many people accessed project) Bluespec Board Support Packages   Updated on: 27-Jun-2008   VLM: 78 Common components needed to instantiate Bluespec designs on common FPGA, ASIC, and simulation platforms. For example, wrappers for different memories, memory controllers, and peripherals.   Category :: Library Language :: Other   extension_pack   Updated on: 14-Sep-2006   VLM: 117 a set of low level functions and procedures to expand upon your VHDL   Category :: Library Language :: VHDL Phaze :: Design done Development status :: Production/Stable   gh vhdl library   Updated on: 08-Nov-2008   VLM: 863 A VHDL library of counters, shift registers, and other MSI parts as well as the a dual port RAM, FIFO, the CIC filter, a CORDIC, FIR Filter and TVFD filter   Category :: Library Language :: VHDL Phaze :: Design done Development status :: Production/Stable   openVeriFLA - FPGA logic analyzer   Updated on: 03-Mar-2008   VLM: 246 No description provided   Category :: Library Language :: Verilog License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   Random Number Generator Library   Updated on: 14-Oct-2007   VLM: 298 A library of functions to generate random numbers with different distributions. The functions are intended for use in VHDL test benches where random data is required.   Category :: Library Language :: VHDL License :: GPL Phaze :: Design done Development status :: Production/Stable   Robot Control Library   Updated on: 14-Feb-2007   VLM: 288 In this project we assemble and implement common control elements into OPB/WishBone compliant ip modules. The main objective is robot control, sensor or actuator modules such as PID, Quadrature encoder, PWM generator, Stepper control and Spline g...   Category :: Library Language :: VHDL   SRT Division Unit   Updated on: 28-Aug-2007   VLM: 92 This is a planned collection of synthesizable hardware dividers at radix-2, radix-4, radix-16. All use the redundant number system for intermediary results to avoid the carry chain. All designs are fully parameteriseable and synthesizable. Th...   Category :: Library Language :: Verilog Development status :: Planning