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Category :: Crypto core We use a few icons to help identify projects: Indicates new project, that has been added in the last 30 days. Indicates project that is ready to use Indicates a WISHBONE Compliant Core VLM = Visits Last Month (how many people accessed project) AES (Rijndael) IP Core   Updated on: 22-May-2007   VLM: 761 AES (Rijndael) IP Core. Complete with cipher and inverse cipher and key expansion block. Everything written in Verilog - high performace, small area.   Category :: Crypto core Language :: Verilog Development status :: Production/Stable   128/192 AES   Updated on: 19-Sep-2005   VLM: 419 A 128 bits and a 192 bits key length AES coprocessor focusing on very low area applications. The 128 bit implementation takes about 500 cycles to encrypt/decrypt a block. The 192 bit implementation takes about 280 cycles to encrypt/decrypt a b...   Category :: Crypto core Language :: Other Language :: Verilog Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   3DES (Triple DES) / DES (VHDL)   Updated on: 01-Dec-2006   VLM: 327 A VHDL implementation of Triple-DES (pipelined) and DES cryptographic algorithms, as recommended by NIST.   Category :: Crypto core Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable   AES (Rijndael)   Updated on: 04-Dec-2002   VLM: 848 AES (Rijndael) is private key symmetric block cipher that can process data blocks of 128 bits, using cipher keys with lengths of 128, 192, 256 bits.   Category :: Crypto core Development status :: Planning   AES core modules   Updated on: 15-May-2007   VLM: 459 AES modules in VHDL. This is base implementation of algorithm described in http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf   Category :: Crypto core Language :: VHDL Phaze :: Design done Phaze :: Specification done Development status :: Production/Stable   AES128   Updated on: 28-Dec-2004   VLM: 454 Advanced Encryption Standard Cryptographic Core   Category :: Crypto core Language :: VHDL License :: LGPL Phaze :: Design done Development status :: Production/Stable   Basic DES Crypto Core   Updated on: 15-Oct-2005   VLM: 229 Fast, small ECB mode DES encryption and decryption. Can be daisychained to implement TripleDES. Additional logic required for CFB, CBC, and other modes.   Category :: Crypto core Language :: VHDL Development status :: Production/Stable   Basic RSA Encryption Engine   Updated on: 15-Oct-2005   VLM: 281 A no-frills implementation of the RSA Public Key Encryption algorithm. The design is intended as an exercise in hardware design, and meets only two requirements: 1) It must work. 2) It must fit within a commercially available FPGA.   Category :: Crypto core Language :: VHDL Development status :: Production/Stable   Bluespec MD6   Updated on: 28-Oct-2008   VLM: 312 The first hardware implementation, a novel hashing algorithm by Ron Rivest. This algorithm is highly parallel. This code has been proven on the XUP platform, on which hashing speeds of 233 MB/s have been achieved.   Category :: Crypto core Language :: Other Phaze :: FPGA proven Development status :: Beta   Camellia cores   Updated on: 23-Jun-2008   VLM: 99 VHDL implementations of Camellia cipher. All block size (128, 192, 256) are supported.   Category :: Crypto core Language :: VHDL License :: GPL Development status :: Beta   Crypto-PAn   Updated on: 17-Feb-2007   VLM: 102 A hardware implementation of Prefix-Preserving IP Address Anonymization. The core makes use of a fully pipelined 128-bit AES (Rijndael) cipher engine as the underlying pseudorandom function, supports online key changes, and is capable of line rat...   Category :: Crypto core Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   DES/Triple DES IP Cores   Updated on: 22-May-2007   VLM: 481 Traditional DES and Triple DES IP Cores.   Category :: Crypto core Language :: Verilog Development status :: Production/Stable   High Radix Montgomery RSA Crypto Core   Updated on: 14-Oct-2001   VLM: 155 RSA Cryptosystem is widely used in information technology. It encrypts and decrypts messages using public key mechanism. The security of this cryptosystem is based on the fact that it's very difficult to factorize large prime number.   Category :: Crypto core Development status :: Planning   IDEA core   Updated on: 03-Jul-2002   VLM: 153 The IDEA (International Data Encryption Algoritma) is a symetric-key block cipher that can encrypts 64-bits plaintexs to 64-bit ciphertexts using a 128-bit key, used for secure communications. It is also can do descryption with the same block ...   Category :: Crypto core Development status :: Planning   Mini AES   Updated on: 28-Dec-2005   VLM: 236 Advanced Encryption Standard (AES) implementation with small area/resources utilization.   Category :: Crypto core Language :: VHDL Phaze :: Design done Development status :: Alpha   RSA Processor   Updated on: 14-Oct-2001   VLM: 206 RSA ( Rivest Shamir Adleman )is crypthograph system that used to give a secret information and digital signature.   Category :: Crypto core Development status :: Planning   SHA cores   Updated on: 20-May-2004   VLM: 177 This is a collection of SHA(Secure Hash Algorithm) IP cores.   Category :: Crypto core Language :: Verilog License :: LGPL Phaze :: Design done Development status :: Beta   SHA1 Secure Hash Algorithm   Updated on: 08-Jul-2004   VLM: 183 Verilog Implementation of SHA1 Secure Hash Algorithm   Category :: Crypto core Development status :: Alpha   Simple Camellia Crypto Core   Updated on: 26-Oct-2004   VLM: 83 The Simple Camellia Crypto Core is implementation of the Camellia encryption Algorithm. It support with 128 bit data lenght and 128 bit key. it works in CBC mode.   Category :: Crypto core Language :: VHDL   SystemC/Verilog DES   Updated on: 19-Sep-2005   VLM: 174 An area improved DES coprocessor and his equivalent Verilog description.   Category :: Crypto core Language :: Other Language :: Verilog Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   SystemC/Verilog MD5   Updated on: 15-Sep-2005   VLM: 176 A MD5 hash algorithm implementation in SystemC, including the equivalent synthesizable Verilog translation   Category :: Crypto core Language :: Other Language :: Verilog License :: LGPL Phaze :: FPGA proven Development status :: Production/Stable   twofish 128/192/256   Updated on: 08-May-2006   VLM: 144 VHDL implementation of the twofish cipher for 128,192 and 256 bit keys.   Category :: Crypto core Language :: VHDL License :: GPL Phaze :: Design done Development status :: Production/Stable   Twofish Core   Updated on: 17-Oct-2002   VLM: 122 Twofish is one of five finalists for the AES (Advanced Encryption Standard) competition held by the National Institute of Standard and Technology (NIST). Twofish is described in a 128-bit chiper that supports key-length of 128 ,192 or 256-bits...   Category :: Crypto core Development status :: Beta   XTEA Crypto Core   Updated on: 14-Apr-2006   VLM: 127 This is a Verlog implementation of the XTEA encryption algorithm - see http://en.wikipedia.org/wiki/XTEA.   Category :: Crypto core Language :: Verilog License :: LGPL Phaze :: FPGA proven Development status :: Production/Stable