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Category :: Arithmetic core We use a few icons to help identify projects: Indicates new project, that has been added in the last 30 days. Indicates project that is ready to use Indicates a WISHBONE Compliant Core VLM = Visits Last Month (how many people accessed project) 5x4Gbps CRC generator designed with standard cells   Updated on: 05-May-2004   VLM: 291 The design can handle 5 different channels at an input rate of 2Gbps each (the total output throughput is 5x4Gbps.) The generated CRCs are compatible with the 32-bit Ethernet standards. The circuit has been implemented with standard cells ...   Category :: Arithmetic core Language :: VHDL License :: GPL Development status :: Production/Stable   Binary to BCD conversions, with LED display driver   Updated on: 25-Oct-2005   VLM: 370 Modules for converting binary input to Binary Coded Decimal (BCD) output, and for converting Binary Coded Decimal input to binary output. Tested in hardware. Parameterized Verilog.   Category :: Arithmetic core Development status :: Production/Stable   CF Cordic   Updated on: 08-May-2008   VLM: 372 Confluence generated cordics.   Category :: Arithmetic core Development status :: Production/Stable   CF FFT   Updated on: 08-May-2008   VLM: 722 Confluence generated FFTs (Fast Fourier Transforms).   Category :: Arithmetic core Development status :: Production/Stable   CF Floating Point Multiplier   Updated on: 08-May-2008   VLM: 375 Confluence generated floating point multipliers.   Category :: Arithmetic core Development status :: Production/Stable   CORDIC core   Updated on: 14-Feb-2004   VLM: 1026 The CORDIC (COordinate Rotation on a DIgital Computer) algorithm is an iterative algorithm to evaluate many mathematical functions, such as trigonometrically functions, hyperbolic functions and planar rotations.   Category :: Arithmetic core Language :: VHDL Phaze :: Design done Phaze :: FPGA proven Development status :: Production/Stable   DCT - Discrete Cosine Transformer   Updated on: 13-Oct-2001   VLM: 635 Most video compression standards such as HDTV, H.261, JPEG and MPEG use Discrete Cosine Transform (DCT) as a standard transform-coding scheme.   Category :: Arithmetic core Development status :: Beta   Discrete Cosine Transform core   Updated on: 01-Jun-2008   VLM: 444 Parallel implementation of 2D DCT in VHDL. Currently works on 8 bit input data using 12 bit DCT coefficients. Multiplier-less design, distributed arithmetic used instead.   Category :: Arithmetic core Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable   FPU   Updated on: 29-Jun-2008   VLM: 1401 The floating point unit (FPU) implemented during this project, is a 32-bit processing unit, which does arithmetic operations on floating point numbers. The FPU complies fully with the IEEE 754 Standard.   Category :: Arithmetic core Category :: Coprocessor Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable   Hardware Division Units   Updated on: 20-Jan-2004   VLM: 397 This is a collection of hardware divider cores.   Category :: Arithmetic core Development status :: Production/Stable   HCSA adder and Generic ALU based on HCSA   Updated on: 09-Apr-2003   VLM: 178 Adder is a BASE of mostly everything in the Digital World and its characteristics have a huge impact on the Digital Circuit at the whole. Hierarchical Carry Save Algorithm (HCSA) is a modification of one of the three well known adder algorithms...   Category :: Arithmetic core Development status :: Production/Stable   HIERARCHICAL Integer Multiplier unit   Updated on: 17-Jul-2003   VLM: 187 One of the Implementations of Completely Asyncronous unsigned(signed) integer multiplication algorithms. These IPs could be embeded into any of the design where the multiplication is supposed to be done for 1 clock step, such as DSP, RISC and us...   Category :: Arithmetic core Development status :: Production/Stable   PYRAMID Integer Multiplier unit   Updated on: 17-Jul-2003   VLM: 190 One of the Implementations of Completely Asyncronous unsigned(signed) integer multiplication algorithms. These IPs could be embeded into any of the design where the multiplication is supposed to be done for 1 clock step, such as DSP, RISC and us...   Category :: Arithmetic core Development status :: Production/Stable   radix 4 complex fft   Updated on: 11-Sep-2003   VLM: 452 Configurable radix 4 complex fft   Category :: Arithmetic core Development status :: Production/Stable   Single Clock Unsigned Division Algorithm   Updated on: 23-Apr-2004   VLM: 432 Preface Now two division algorithms are wide spread in computing: restoring and non-restoring algorithms. They consider that both algorithms may be used in sequential calculation scheme, when one digit of the result is achieved during o...   Category :: Arithmetic core Language :: VHDL Phaze :: Design done Phaze :: Specification done Development status :: Production/Stable   True matrix 3x3 multiplier   Updated on: 26-Feb-2007   VLM: 357 Here is the direct 3x3 matrix multiplication. Precision of matrix factors is 10-E4. Trnasform operations were verifyied by the comparing with Matlab's equation. Testbench is attached. Resource utilization by the core with 10-bit input data for...   Category :: Arithmetic core Language :: VHDL License :: LGPL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   Unsigned serial divider   Updated on: 03-Mar-2007   VLM: 292 Parameterized module performs unsigned division operation. Parameters determine the size of the quotient, divisor and dividend. Can be used to produce fractional results as well. Takes multiple clock cycles to execute, since it uses serial ope...   Category :: Arithmetic core Development status :: Production/Stable   Viterbi HDL Code Generator   Updated on: 10-May-2006   VLM: 473 This is one HDL code generator of some kinds of Viterbi decoders. Now it can only generate Verilog HDL code. I hope somebody will improve this generator for the special applications. It would be licensed under GPL, I think. But the HDL code will ...   Category :: Arithmetic core Language :: Other License :: GPL Phaze :: Design done Development status :: Beta