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Best rated projects We use a few icons to help identify projects: Indicates new project, that has been added in the last 30 days. Indicates project that is ready to use Indicates a WISHBONE Compliant Core R = Rating (calculated from number of visits, downloads and activity) OpenRISC 1000   Updated on: 17-Jul-2008   R: 7045 OpenRISC 1000 is an architecture of a family of open source, synthesizable RISC microprocessor cores. It is a 32-bit load and store RISC architecture designed with emphasis on speed, compact instruction set and scalability. OpenRISC 1000 targets ...   Category :: Microprocessor Language :: Verilog License :: LGPL Phaze :: ASIC proven Standard :: Wishbone compliant core Development status :: Production/Stable   JOP: a Java Optimized Processor   Updated on: 25-Jul-2008   R: 3072 JOP is the implementation of the Java Virtual Machine (JVM) as concrete machine in hardware. The design is full synthesizable and fits in low-cost FPGA devices from Altera and Xilinx.   Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   Ethernet MAC 10/100 Mbps   Updated on: 24-Sep-2007   R: 2356 The Ethernet MAC (Media Access Control), sublevel within the Data Link Layer of the OSI reference model. This core is designed for implementation of CSMA/CD LAN in accordance with the IEEE 802.3 standards. The MAC is the portion of ethernet core ...   Category :: Communication controller Standard :: Wishbone compliant core Development status :: Production/Stable   Plasma - most MIPS I(TM) opcodes   Updated on: 24-Jul-2008   R: 1768 The Plasma CPU core supports interrupts and all MIPS I(TM) user mode instructions except unaligned load and store operations.   Category :: Microprocessor Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable   I2C controller core   Updated on: 09-Apr-2008   R: 1655 I2C is a two-wire, bidirectional serials bus that provide a simple, efficient method of data exchange between devices.   Category :: Communication controller Language :: Verilog Language :: VHDL Phaze :: ASIC proven Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   USB 1.1 Host and Function IP core   Updated on: 22-Mar-2008   R: 1618 USB 1.1 host and function modes of operation. Full (12Mbps) and low speed (1.5Mbps) operation. Isochronous data transfers supported. Function mode supports four endpoints.   Category :: Communication controller Language :: Verilog License :: LGPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   ZPU - the worlds smallest 32 bit CPU with GCC toolchain   Updated on: 25-Jun-2008   R: 1251 This is the worlds smallest 32 bit CPU with a GCC/GDB toolchain, operating systems support(eCos), simulator, etc. Multiple VHDL implementations available. BSD license, except for those pieces to the puzzle that already have another open so...   Category :: Microprocessor Language :: VHDL Phaze :: Design done Phaze :: FPGA proven Phaze :: Specification done Standard :: Wishbone compliant core Development status :: Beta Development status :: Production/Stable   FPU   Updated on: 29-Jun-2008   R: 1220 The floating point unit (FPU) implemented during this project, is a 32-bit processing unit, which does arithmetic operations on floating point numbers. The FPU complies fully with the IEEE 754 Standard.   Category :: Arithmetic core Category :: Coprocessor Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable   CAN Protocol Controller   Updated on: 30-Apr-2008   R: 1018 CAN (Controller Area Network) is a widely used control network protocol. Typical Apllications are automation and in-car networking. The project aims to develop an open source implementation of CAN Protcol Version 2.0 Part A and B. It should be...   Category :: Communication controller Standard :: Wishbone compliant core Development status :: Production/Stable   Micro FPGA Board   Updated on: 15-Oct-2001   R: 1017 Micro FPGA board is a stand alone, low cost, do-it-yourself board. All components are possible to get from a local electronics shop (with possible exception of Virtex part). Board includes one Xilinx Virtex XCV100 chip.   Category :: Prototype board Development status :: Production/Stable   MCPU - A minimal CPU for a CPLD   Updated on: 21-Mar-2008   R: 942 mcpu is a minimal cpu designed to fit into a 32 macrocell CPLD. 4 Instructions and access to 64 bytes of memory are supported. Sourcecode is provided in VHDL and Verilog and occupies only a single printed page.   Category :: Microprocessor Language :: Verilog Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Mature Development status :: Production/Stable   a VHDL 16550 UART core   Updated on: 22-Jul-2008   R: 940 a 16550 compatible UART in VHDL   Category :: Communication controller Dependencies :: Other cores Language :: VHDL Phaze :: Design done Development status :: Production/Stable   USB 2.0 Function Core   Updated on: 27-Jun-2005   R: 855 USB 2.0 compliant core which allows data transfers of 480 Mb/s.   Category :: Communication controller Language :: Verilog Standard :: Wishbone compliant core Development status :: Production/Stable   Bluespec H.264 Decoder   Updated on: 07-Jul-2008   R: 850 BSV implementation of H.264 Video decoder.   Category :: Video controller Language :: Other Phaze :: FPGA proven Development status :: Beta   VGA/LCD Controller   Updated on: 13-May-2004   R: 844 The OpenCores VGA/LCD Controller core is a WISHBONE rev.B3 compliant embedded VGA core capable of driving CRT and LCD displays.   Category :: Video controller Language :: Verilog Phaze :: ASIC proven Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   Wishbone LPC Host and Peripheral Bridge   Updated on: 25-Jul-2008   R: 834 Wishbone to Low-Pin-Count (LPC) bridge. Supports I/O Read/Write cycles, Memory Read/Write cycles, and Firmware Memory Read/Write cycles. Wishbone Slave to LPC Host, and LPC Peripheral to Wishbone Master modules are provided. Serial IRQ support ...   Category :: Communication controller Language :: Verilog License :: LGPL Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable